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Semiconductor process, device, and circuit simulation plays a significant role in the development of integrated circuit technology, providing quick prototyping and quantities not easily measured. Predictive models allow optimization of chip designs and are an essential component of the technology design process. As semiconductor devices shrink into the deep-submicron regime, device simulation faces...
The complexity of multi-level cache hierarchies simulation is much more complicated than that of single-level cache simulation, so that it is highly desirable to develop some efficient simulation methods for multi-level cache hierarchies performance analysis. A one pass multi-level unified cache hierarchies simulation method is developed based on stack model and inclusion properties. Recently, many...
Write-buffers have a significant impact on performance, especially in wide-issue superscalar systems with write-through caching. We develop fast efficient simulation methods for evaluating multiple write-buffer configurations together in a single-pass. Our results are also applicable for the simulation of other buffer structures. We first consider simulating non-coalescing write-buffers. We show that...
HASE is a hierarchical computer architectural design and simulation environment which allows a computer architecture and its implementation to be represented graphically at several different levels of abstraction. Class inheritance is used to factor out common behaviour, for example, producer/consumer synchronisations, queue and statistics functions inherited by the memory, bus and function unit hierarchies...
The authors have designed and built HARP (Hermite AcceleratoR Pipeline)-1, a special-purpose computer for solving astronomical N-body problems with high accuracy using the Hermite integrator. The Hermite integrator uses analytically calculated time derivatives of the acceleration, in addition to the acceleration, to integrate orbits of particles. HARP-I has a 24-stage pipeline to perform the calculation...
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