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This paper describes a majority logic gate circuit on a “single-dopant” device. The single-dopant device that has been receiving increasing attention in recent years is one of atomic scale solid-state device and can be a practical platform for a single-electron circuit. We here aim to fabricate actual single-dopant majority logic circuits with deterministic doping method. For this, we design a possible...
In this work, we study the resistive switching characteristics of two different resistive switching memory devices (SiNx and HfOx) with SiO2 tunnel barrier. The switching of the former and the latter is based on the movement of hydrogen ion and oxygen vacancies, respectively. For Cu/SiNx/SiO2/p+-Si device, the operating current is drastically reduced and nonlinearity of LRS is increased compared to...
We report for ultra-thin Si tunnelling diodes that negative differential conductance (NDC) is dominated by the excess current at room temperature. This is attributed to the gap-states induced by the co-dopants in the pn junction. First-principles simulation shows that the presence of co-dopants in the pn junction region leads to an increase in the interband tunnelling current by two orders of magnitude...
A thorough understanding on how to design and to manufacture a face-tunneling TFET (f-TFET) has been provided. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, f-TFET can be enhanced in its current. This work shows I0„ of f-TFET with one-order magnitude I„n enhancement than that of point-TFET(control), and the longer the gate length is, the higher the becomes...
I will give an overview of our recent work on the integration of III-V semiconductor nano-structures on silicon (Si) for electronic devices. The template-assisted selective epitaxy (TASE) used to monolithically integrate high crystal quality III-V nanostructures on Si is introduced. The challenges and recent progress of the development of nanoscale III-V MOSFETs and Tunnel FETs is discussed and a...
The polycrystalline silicon (poly-Si) gate-all-around (GAA) nanowire transistors with 10nm scale width were fabricated under precise width control. The nanowire width is 10nm scale. Measured characteristics show smaller threshold voltage and drain current variability than that of previously reported poly-Si nanowire transistors.
We have investigated dynamic characteristics of ferroelectric Hf02 (FE-HfÓ2) by considering multiple domain (MD) and linear domain-domain interaction. By using the calibrated MD model, experimental dynamic responses of FE-HfO2 can precisely reproduced, for the first time. Input voltage amplitude (Vin) and external resistance (R) dependences of dynamic responses in FE-HfO2 revealed that dynamic term...
In this work, Work-Function Variation (WFV) are studied on 5 nm node gate-all-around (GAA) Vertical Nanoplate FET (NP VFET) in 6-T SRAM using Technology computer-aided design (TCAD) simulation. As WFV effects become intensified, we investigate the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of NP VFET in SRAM bit cells.
In this paper, we show a possibility of Si resonant plasma-wave transistor (R-PWT) as THz detector. Κ the channel mobility of strained Si R-PWT is 400 cm·V−1·s1, R-PWT can be operated as THz detector when channel length l= 21–28 nm.
Grating coupler based on 220 nm Si-on-insulator (SOI) substrate was designed and optimized for operation at 2 μm wavelength targeting telecommunication application. Decent coupling efficiency of around 18% is achieved, which is consistent with the simulation results and can be employed in 2 μτη-based photonic integrated circuit.
We report n-FinFETs with a high drive current of 108 Aim and the best SS of 138 mV/dec. A higher drive current was achieved by the reduction of series S/D resistance. NiGeSn/n+-GeSn contact formation was done by rapid thermal annealing below 400 °C. Contact resistivity was characterized by circular transmission line model. The contact resistance decreases with the carrier concentration or Sn fraction...
Nano-wedge structured resistive switching memory is fabricated through modifying bottom electrode structure and the DC characteristics of devices are analyzed. Excellent data storage capability is proved through retention test by setting at high temperature over 104 seconds in both low and high resistance states (LRS and HRS). Endurance test is also performed to demonstrate outstanding characteristics...
It has been reported that erbium (Er) is a source of optical emission at λ=1.54 pm due to 4I13/2 →4I15/2 transition of Er3+. A method of oxygen (O) codoping with Er has attracted attention as a candidate for obtaining more efficient optical gain by forming Er:O complex. Although several simulations predict the equilibrium structure of Er:O complex, it is difficult to understand experimentally how...
The temperature dependence of MOSFET and TFET-based pH sensitive ISFET was investigated through TCAD device simulation. The transfer characteristics and the pH sensitivities of both devices at various temperature were compared. TFET-based ISFET exhibits superior thermal stability in contrast with the MOSFET-based ISFET due to the difference of conduction mechanism.
Luminescence of erbium in silicon has been intensively explored in the past in the high power emission regime, but its employment for manufacturability of active components for silicon photonics proved unfeasible. We explore the room-temperature photoluminescence (PL) at the telecomm wavelength of very low implantation doses of ErOx in Si for accessing few photon regime towards single photon emission...
In this paper, the two Negative Bias Temperature Instability (NBTI) framework components are divided with interface trap generation (Δ Vit) and hole trapping in pre-existing defects (Δ Vht). The threshold voltage shift (ΔVT) contribution is verified by two divided components and studied independently. The impact of inter layer (IL) thickness is simulated under NBTI stress using technology computer-aided...
In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.
We demonstrate the single-shot spin read-out of single donors and few-donor clusters, positioned with atomic precision by scanning tunneling microscopy (STM) in atomically engineered silicon devices [1-3]. In donor clusters, we measure spin lifetimes of up to half a minute, recorded at a read-out fidelity of up to 99.8% [2]. Importantly, measuring spin relaxations rates of electrons bound to a single...
We have recently reported single-electron tunneling (SET) via a-few-donor QDs at high temperatures in high-concentration selectively-doped SOI-FETs. A central QD works by SET mechanism above 150 Κ at small source-drain bias due to enhanced tunnel barrier. For tuning the tunnel barrier, it becomes critical to understand the impact of the donor-QD location on the SET transport. Here, we report the possibility...
Scaling of silicon MOSFETs has been predicted to go around 10 nm and below. For such a small transistor a gate-all-around nanowire is regarded as an ideal geometry to maintain gate control. On the other hand, such downsizing and excellent gate control has provided opportunities to control individual electrons one by one by placing gates on top of the nanowire to define charge islands and potential...
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