The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.
In this work, we compare parasitic components between lateral nanowire-FET (LFET) and vertical nanowire-FET (VFET) based on ITRS 2015 using 3D Technology Computer-aided Design (TCAD). We compare the parasitic resistances and capacitances in accordance with channel thickness. Further, we analyzed the effects of parasitic components on device performance and proposed the direction of device scaling.
This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent Vth controllability. Low-temperature operation enables higher drive...
Novel thin film transistor based on a graphene-ZnO Schottky junction has been demonstrated for display driver circuit applications. High transmittance over 80% in visible light wavelengths with a high on-off ratio over 104 are the merits of this device. All device fabrication processes completed at a temperature below 200°C will provide a unique advantage in the flexible display applications. The...
This paper demonstrates and experimentally reports the highest ever performance boosting in strained silicon-nanowire homojunction TFETs with negative capacitance, provided by matched PZT capacitors. Outstanding enhancements of Ion, gm, and overdrive are analyzed and explained by most effective reduction of body factor, m < 1, especially for Vg>Vt, which greatly amplify the control on the surface...
Aiming at performance enhancements and robust reliability design of mono-layer transition-metal dichalcogenide (TMD) tunneling FET(TFET), W vacancy(Vw) defect is systematically studied in this work. Impacts of Vw defect's positions are characterized in WSe2 TTETs by using rigorous ab initio simulations. It is found that Vw defect that locates in the tunnel junction will increase Ion, while it has...
Thermal-management design for power devices by placing the 2D graphene heat spreader (GHS) at the backside of collector-up heteroj unction bipolar transistors (HBTs) is presented. Temperature distribution in the GHS and the application of these spreaders to ameliorate thermal-coupling effects on multi-finger transistors were discussed. Compared to the npn device, the pnp device exhibits greater thermal-stability...
In this paper, we have investigated RC delay not only on single channel but also on multi-channels in lateral FET (LFET) and vertical FET (VFET). It has verified that there is always constant for SCEs regardless of the number of channels. Since all structures have the same gate length and spacer length, they have the same gate controllability. On the other hand, RC delay depends on the structure....
We propose a novel vertical tunnel FET of band-to-band tunneling aligned with the gate electric field. Simulation results show high drive current and extremely sharp subthreshold swing due to excellent gate control over the tunnel junction. OFF state leakage via source-to-drain tunneling is much suppressed by the spacer layer between the source and drain layers. Furthermore, this device is fully compatible...
Accurate evaluation of Self Heating Effects in highly down-scaled devices becomes essential for improved performance and reliability. However, complex structure of BEOL causes analysis of SHEs to be difficult To remove the difficulty, based on Rent's rule to obtain interconnect density function, effective thermal conductivity of BEOL versus metal volume density and average aspect ratio (p) was calculated...
Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure...
In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, and transient characteristics are analyzed. The FBFET has steep switching property and low off current. We design an inverter that can low power operate with the FBFET. By using the FBFET, the stand-by current is effectively suppressed...
In this work, we study the resistive switching characteristics of two different resistive switching memory devices (SiNx and HfOx) with SiO2 tunnel barrier. The switching of the former and the latter is based on the movement of hydrogen ion and oxygen vacancies, respectively. For Cu/SiNx/SiO2/p+-Si device, the operating current is drastically reduced and nonlinearity of LRS is increased compared to...
In this work, Work-Function Variation (WFV) are studied on 5 nm node gate-all-around (GAA) Vertical Nanoplate FET (NP VFET) in 6-T SRAM using Technology computer-aided design (TCAD) simulation. As WFV effects become intensified, we investigate the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of NP VFET in SRAM bit cells.
Simple 2D scaling of semiconductor devices by “Moore's law” will not work well soon to improve the performances and power efficiencies due to tight physical directional limits. System integrations, however, might continue to advance further by 3D structural evolutions either in monolithic on-chip integrations or heterogeneous off-chip stacks. Accelerated implementations of new architectures and new...
We report the impact of device design parameters on the saturation voltages (VDSAT) and thereby on analog performance of the Tunnel FETs (TFET). As the drain bias (VDS) increases, the device initially enters a soft saturation and later into a deep saturation state, both at a constant difference between the gate-drain bias (VGD)· An increase in source (drain) doping decreases (increases) the soft saturation...
In this paper, we will review the current challenges and advancements to continue standard device scaling beyond the 5nm technology node. Apart from the introduction of new materials and device concepts, we will also address the trend towards more heterogeneous systems requiring close interaction between the technology and system optimization.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.