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An inhibition part of synapse-neuron connection is indispensable in a neuromorphic system for hardware implementation of artificial intelligence. First, when the system operates with the winner takes all method, a lateral inhibition is required to permit one neuron firing, thereby preventing other neurons from firing. In addition, in order to implement the negative weight, an inhibition part, which...
Thermal-management design for power devices by placing the 2D graphene heat spreader (GHS) at the backside of collector-up heteroj unction bipolar transistors (HBTs) is presented. Temperature distribution in the GHS and the application of these spreaders to ameliorate thermal-coupling effects on multi-finger transistors were discussed. Compared to the npn device, the pnp device exhibits greater thermal-stability...
We have successfully exploited multi-dimensional spaces of concentrations of the interstitial species, Si and Ge, geometries and compositions of the starting SiGe nano-pillar, and sources of Si interstitials (the Si3N4 and Si encapsulation layers) to create new classes of exciting optical and electronic devices such as single-electron tunneling devices, wavelength-tunable photodetectors, and MOSFETs.
In this paper, we have investigated RC delay not only on single channel but also on multi-channels in lateral FET (LFET) and vertical FET (VFET). It has verified that there is always constant for SCEs regardless of the number of channels. Since all structures have the same gate length and spacer length, they have the same gate controllability. On the other hand, RC delay depends on the structure....
Self-heating effects (SHEs) were studied on the vertical nanoplate-shaped gate-all-around (GAA) FETs (vNPFETs) as a target of 5nm node technology. The thermal properties are compared between face-up and face-down configuration. Decreasing the channel width is vulnerable to both configurations in terms of SHEs due to the reduced area of heat dissipation. It is well known that the SHE is alleviated...
In this study, the effects of nitride trap layer properties on location of charge centroid in charge-trap flash (CTF) memory are closely investigated. In the operations of CTF memories, charges tunnel into the nitride layer through thin oxide, unlike the floating-gate (FG) type flash memory where the charges are stored in the conductive poly-crystalline Si. Deeper understanding of distribution of...
We propose a novel vertical tunnel FET of band-to-band tunneling aligned with the gate electric field. Simulation results show high drive current and extremely sharp subthreshold swing due to excellent gate control over the tunnel junction. OFF state leakage via source-to-drain tunneling is much suppressed by the spacer layer between the source and drain layers. Furthermore, this device is fully compatible...
This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10...
Metallic junction engineering and tunnel field-effect architecture are the two major techniques to resolve the power dissipation issue of future transistor technologies. This work explores the on-off switching of metal source tunnel field-effect transistors. Two prime factors, source workfunction and dopants segregation, are utilized to optimize the subthreshold swing and on-current for serving as...
In this paper, the Self-Heating Effects in Vertical FETs(VFET) have been investigated according to device geometry. It is demonstrated that the temperature of the device increases by using a low-k dielectric and an air gap between the metal lines. In addition, when air spacers are used, the lattice temperature is further increased and the on current reduction ratio increases compared to the common...
With relaxed SiGe, this work elaborates the correlation of semiconductor band edges and source-drain metal workfunction for the electrical characteristics of p- and n-channel FETs based on numerical simulations. For a given high workfunction source-drain metal, it is found that the on-current, threshold voltage and off-current of p-channel devices increase monotonously with the Ge mole fraction. The...
Resonant tunneling diodes (RTD) are widely used in nano electronics due to their nonlinear properties. In this work, Metal-Insulator-Insulator-Insulator-Semiconductor (MIIIS) devices were fabricated using a gate stack of atomic-layer deposited (ALD) high-k oxides and experimental proof of Resonant Tunneling was obtained due to three Negative Differential Resistance (NDR) zones.
In this work we study the random telegraph noise (RTN) characteristics of short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors. The test devices were fabricated with I-line-based lithography in combination with novel spacer-etching techniques for aggressively shrinking the channel dimension. Based on the tiny nanowire channel and short-channel length, we are able...
Accurate evaluation of Self Heating Effects in highly down-scaled devices becomes essential for improved performance and reliability. However, complex structure of BEOL causes analysis of SHEs to be difficult To remove the difficulty, based on Rent's rule to obtain interconnect density function, effective thermal conductivity of BEOL versus metal volume density and average aspect ratio (p) was calculated...
This work investigates the impact of fin-LER on the subthreshold characteristics of the negative-capacitance FinFETs by TCAD atomistic simulation coupled with the Landau-Khalatnikov equation. Our study indicates that the variability for Vt, SS and DIBL can be suppressed by the negative-capacitance feedback mechanism. The ferroelectric layer exhibits larger gate voltage amplification for the device...
Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure...
A high peak hole mobility of 412 cm2/V-sec at Ninv=1.8×1012 cm−2, a very low Jg of ∼10−4 A/cm2 at Vg=Vfb+1 V and an ultralow EOT of 0.53 nm in Ge pMOSFETs are simultaneously achieved by high-k/0D-HKVGe02 gate stack with suitable treatments. The content of Ge+1 and Ge+2 in GeOx layer are re-oxidized to higher oxidation state by gettered oxygen, which is captured by OD-HfOx from GeOx. The proposed gate...
In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, and transient characteristics are analyzed. The FBFET has steep switching property and low off current. We design an inverter that can low power operate with the FBFET. By using the FBFET, the stand-by current is effectively suppressed...
In order to obtain high channel boosting potential and to reduce a program disturbance in channel stacked type with layer selection by multi-level operation (LSM), a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. To verify the validity of the new method in LSM, TCAD simulations are...
In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word...
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