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This paper shows new insights on the stochastic nature of aging-related timing impact in digital circuits. Varying critical paths through aging trigger the need for aging compensation control loop based on an unsupervised machine learning algorithm. Adaptive Resonance Theory (ART) algorithm is favored for its ability to handle the stability-plasticity dilemma.
This paper presents a methodology for reducing functional test time in subthreshold SoCs targeting ultra-low power (ULP) internet-of-things (IoT) devices. Due to their low operating speed and voltage, subthreshold SoCs require significantly longer time to test than traditional SoCs. The proposed method models trans-threshold correlations to allow high voltage, high speed testing while accurately predicting...
A contemporary high-performance system board is a complex 3D object that may contain dozens of hidden layers, stacked microvias, high density interconnect, with all of the above not contributing to the ease of test and reliability. High-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in the case of now-ubiquitous DDR3 memories. Today, data transmission...
Static test compaction procedures that modify tests perform the modification so as to increase the number of faults that some of the tests detect, thus making other tests unnecessary. Tests that become unnecessary are removed from the test set without reducing the fault coverage. This paper describes a static test compaction procedure of this type for transition faults that has the following additional...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
Localized small delay defects, for example due to degraded transistor drive strength caused by a broken fin, are a growing concern in current FinFET and emerging gate all around (GAA) technologies. Such defects are currently targeted by timing-aware Transition Delay Fault (TDF) tests that aim to test the target nodes along the longest path. The resulting tests often require considerable test generation...
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