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Error tolerance techniques are widely used to protect processor pipelines from variation induced timing errors. In this paper, we propose two standard cell library tuning techniques to optimize error tolerant processor pipelines for power and area savings. The design utilizes positive slack available in the pipeline stages and re-distributes it to the preceding error-prone critical paths using slack...
Engineering change orders (ECO) are small changes in the design due to last minute bug fixes or spec changes. In this paper, we focus on functional ECO in a logic design and try to construct the new logic function, reusing the existing logic as much as possible. Traditional approaches try to find appropriate locations in the original design that their modifications may result in the new functionality...
In safety-critical cyber-physical systems, analog front-ends combined with many-processors are being increasingly employed. An example is an imminent collision detection chip for cars. Such a complex system requires zero downtime and a very high dependability despite aging issues under harsh environmental conditions. By on-line monitoring the health status of the processor cores and taking appropriate...
Network-on-Chip (NoC) serves as an efficient communication framework among the components of Chip MultiProcessors (CMPs). With increasing number of computation intensive applications communication between cores also increases, which creates high congestion resulting in network performance degradation. Handling congestion is a key network management issue in NoC. Hotspots are non-uniform traffic formation...
Building the behavioral model for each analog circuit is an efficient approach for mixed-signal system verification. If an automatic model generator is available, it is useful for designers to reduce the extra efforts. Instead of modeling the relationship between circuit inputs and outputs directly, a divide and conquer approach is proposed in [8] to divide the circuit into several small building...
Several authentication protocols based on Physically Unclonable Functions (PUF) have been proposed to authenticate hardware devices. The preliminary steps of a PUF-based authentication protocol are to obtain and store on a remote server the reference device's secret identifier (known as the PUF response) by the manufacturer. This reference response is compared (accurately or with a small threshold)...
A bio-potential amplifier intended for continuous monitoring of vitals characterized by its long operational lifetime is required to operate at the lowest power budget possible. Moreover, a compact active area directly related to portability is essential. This paper presents a 0.55pW auto gain controlled biopotential amplifier implemented in 65nm 1P7M CMOS for ECG signal classifier SoC. A chopper-stabilized...
Covert channels provide a secret communication medium between two malicious processes to exfiltrate information stealthily that violates the security policy of a system. In this paper, we demonstrate a new covert timing channel attack that exploits the CPU operating frequencies with different power governors in real system environment. In particular, we establish how two colluding processes-a trojan...
A sub-1 V and ultra-low power consumption voltage reference has been implemented in a standard 0.18μm CMOS process, without using resistors and special threshold voltage devices. A temperature coefficient (TC) of 37.8 ppm/°C in a temperature range of −40°C∼60°C is achieved. The supply voltage ranges from 1 V to 3 V, and the line sensitivity (LS) is 0.02%/V. When Vdd is minimum, the supply current...
A low-offset two-stage dynamic comparator has been proposed for parallel multi-channel processing. Low offset is achieved from two aspects: 1st-stage offset cancellation and 2nd-stage offset suppression. A fully dynamic offset cancellation scheme based on current auto-zeroing is adopted to effectively cancel out the 1st-stage offset. It features small area overhead and low energy consumption. For...
Traditional CMOS technology and its continuous down-scaling have been the driving force to improve performance of existing computer architectures. Today, however, both technology and computer architectures are facing challenges that make them incapable of delivering the growing computing performance requirement at pre-defined constraints. This forces the exploration of both novel architectures and...
We are entering the era of thermally-bound computing: Advanced and costly cooling solutions are needed to sustain the high computing densities of high-performance computing equipment. To reduce cooling costs and cooling overprovisioning, dynamic thermal management (DTM) strategies aim at controlling the device temperature by modulating online the performance of processing elements. While operating...
The purpose of the Power-on Reset (POR) circuit is to reset the latches and flip-flops in an SOC to a known state when the supply is ramping up. During power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A common approach is to generate a POR signal by comparing the supply voltage with a reference voltage. Conventional POR circuits also use a resistor divider...
As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers...
A new architecture of charge-pump circuit is discussed that can be used to generate high positive and negative voltages to drive a common load (Load can be capacitive, resistive or both). Basic cell used for charge-pump consists of two phase clock signals, charge transfer NMOS transistors and bootstrapped configuration to boost the gate drive of NMOS transistors. Due to use of NMOS transistors, output...
Line-end cuts in self-aligned double patterning (SADP) process are employed for printing lD-gridded patterns. Redundant via (RV) requires another cut, named RV cut, to be introduced, which may cause coloring conflicts or design rule violations with adjacent line-end cuts. RV insertion should be coordinated together with cut optimization so that maximum number of RVs are inserted while incurring no...
This paper presents a 2×VDD-enabled fully-integrated CMOS low-dropout (LDO) regulator with fast transient response for cost-effective SoC power management applications with elevated-VDD supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high-voltage devices fabrication cost required in a conventional design. Two LV power transistors are...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
High density and low static power exhibited by nonvolatile technologies (NVM) have made them popular candidates in the memory hierarchy, including caches. Writes within a cache set are governed by the access pattern as well as replacement policies, leading to a large write variation. This variation is of concern as it leads to early breakdown of the NVM cells due to large writes thus reducing the...
Pulsed-Index Communication (PIC) is a recent technique for single-channel communication which is based on the principle of transferring the indices of only the ON bits in the form of a series of pulse streams. In this paper, we present a modified version of PIC which is based on the same underlying idea but with key improvements in data rate and reliability. The proposed technique is called Pulsed...
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