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This paper presents a low power, high resolution bio-impedance sensor IC for respiration monitoring application. It contains the dual path instrumentation amplifier (DPIA) including current reusing transconductance amplifier and high gain transimpedance amplifier for high resolution, low power and wide input range bio-impedance measurement. Measured results show that the proposed readout circuit has...
A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and...
A 491.52 MHz CMOS crystal oscillator targeting 5G mobile systems and mmW frequency operation is presented. The high oscillation frequency is imperative to obtain low phase noise in mmW frequency synthesis. The oscillator operates in linear mode controlled by an amplitude feedback loop. Further, a FoM peaking at 256.6 dB with record low EVM contribution for a 5G OFDM signal is achieved, when compared...
This paper presents IC realization of a random forest (RF) machine learning classifier. Algorithm-architecture-circuit is co-optimized to minimize the energy-delay product (EDP). Deterministic subsampling (DSS) and balanced decision trees result in reduced interconnect complexity and avoid irregular memory accesses. Low-swing analog in-memory computations embedded in a standard 6T SRAM enable massively...
A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is...
We present a co-design approach of a near-threshold voltage adaptive microprocessor and power-management unit (PMU). It consists of (i) a microprocessor with in-situ error detection and correction; (ii) an integrated 63-ratio switched-capacitor DC-DC converter; and (iii) an error-based controller which regulates the timing error rate of microprocessor directly instead of indirectly through regulating...
A 7GS/s DDFS MMIC featuring a Two-Times Interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for Random Swapping Thermometer Coding Dynamic Element Matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz...
This paper presents a fractional-N digital PLL that adopts a conventional phase frequency detector (PFD) and a low-power high-gain (>200) time amplifier (TA) in proportional path. Since the TA has narrow input dynamic range, a 7-bit phase interpolator (PI) is used with background multi-point spur calibration. The proposed PLL achieves lower phase noise and better loop gain stability than the bang-bang...
This paper presents a timing error masking-aware ARM Cortex M0 microcontroller system. Timing errors are detected through a timing error detection strategy, consisting of a soft edge flip-flop combined with a transition detector and an error latch. The time borrowing realized through soft edge flip-flops allows data to propagate after the clock edge (timing error masking). Thus operation at the point-of-first-failure...
This work demonstrates a multi-Mode CT ΔΣ ADC in 14nm FinFET Intel Technology. The proposed converter makes use of a novel 5-bit partial DEM technique at 1.25GHz that, in conjunction with an offset current dumping solution, drastically reduces current and area. The ADC reaches a measured DR of 73/71 dB while consuming 8/12 mW for the 9/50 MHz BW modes, respectively.
This paper presents a piezoelectric energy harvesting interface circuit with a technique to broaden the bandwidth by introducing two time delays into the conventional synchronous-electrical-charge-extraction (SECE) scheme. The circuit adaptively adjusts these time delays for maximum power output at off-resonant frequencies. The bandwidth is increased by 71% while the power consumption of the circuit...
A 12bit pipelined ADC based on a class-AB open-loop integrator as residue amplifier is presented. The integrator uses an analog linearization scheme by tuning opposing distortion mechanisms to cancel each other. The gain errors and non-linearity are detected in background with the help of split-ADC calibration technique. The mismatch between the two split-ADCs is minimized by sharing the residue amplifier...
Thermal energy harvesting systems use boost converters for high-efficiency low voltage operation, but lack the ability for low voltage startup without off-chip transformers. We present a cold start system that uses integrated magnetics instead of external transformers in a Meissner Oscillator to start up from ultra low voltages, with a switched capacitor DC-DC circuit for additional voltage gain....
A highly integrated wavelength locking control circuit is presented. It locks the 4Gbps CMOS-Si photonics ring-based transmitter at the maximum optical modulation amplitude (OMA). The control circuit uses direct monitoring of drop-port OMA and a dither-based slope quantizer. It is low-noise and low-offset. Resultantly, a 0.4% (2.2pm, 0.03°C) locking accuracy is achieved with only 15μA of pk-pk OMA...
This paper presents a time-to-digital (TDC) design with large detectable range and fine resolution, combining a ring TDC with a 2-dimentional (2D) Vernier TDC. The detectable range has been greatly increased to 14 bits with the ring structure. A 1-ps resolution was achieving with 2D Vernier architecture. Utilizing the 2nd order ΔΣ modulators (SDM) and a 2D spiral arbiter array, the proposed TDC greatly...
The stacking MOSFET structure composed of low-voltage devices suffers from deteriorated transient response or large footprint area when capacitor-free or dominant pole compensation low dropout (LDO) regulator biases the driver. Due to self-stabilized feature, the proposed stacking MOSFET driving (SMD) technique effectively drives the power stage and greatly reduces noise interference from the noisy...
This paper presents a sub-pA current read-out interface that consists of a series connection of a low-noise current amplifier and a second-order continuous-time Delta-Sigma modulator. Contrary to the approach to the current amplification by means of a series connection of a charge integrator and differentiator, no reset and thus no interruption of the current-to-digital conversion needs to be performed...
This work presents a fully-integrated sub-GHz radio System on Chip (SoC) for Low-Power Wide-Area Networks (LPWAN) and Internet of Things (IoT) applications. The receiver (RX) achieves 77dB blocker rejection and −106dBm sensitivity at 50kbps. The transmitter (TX) features a Switched-Capacitor Power Amplifier (SCPA) that delivers 13.5dBm output power. To fulfil stringent Japanese emission regulation,...
We present here a single-chip platform for Hall-based magnetic sensing. When configured as an angle sensor, the achieved accuracy of 0.5 ° improves the state of the art of Hall-based integrated angle sensors targeting automotive applications (with extended temperature range up to 160 °C. This is achieved thanks to a low offset front-end (< 15 μV) and individual trimming of the Hall element sensitivities...
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