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Real-time 3D ultrasonic imaging requires a matrix of transducer elements with a number of elements that readily exceeds the number of channels of a conventional imaging system. This paper presents an ASIC, realized in a high-voltage 0.18 μm BCDMOS process, that interfaces a piezo-electric transducer array of 24 × 40 elements, directly integrated on top of the ASIC, to an imaging system using only...
We report a system-on-chip (SoC) realised in 130nm CMOS for implantable telemetry systems and mobile health applications featuring 6 neural stimulation channels and acquisition circuits for 9× electrode-based recordings (ExG), 4×/32× photo-plethysmography (PPG), bio-impedance, and temperature. The SoC includes a low-power quad-core processor (34μW/MHz) with sophisticated power and clock management...
A deep learning processor with 8 gated recurrent neural network (RNN) accelerators is proposed in this paper. It features on-chip incremental learning by numerical and local gradient computation enhancement. Extra precision of training is obtained without extending the bit-width. Tri-mode weight access (DMA/FIFO/RAM) improves the throughput during incremental learning. The number multipliers and activation...
This paper presents a calibration technique based on missing-code-detection (MCD) scheme to correct the gain error between the MSB and the LSB array in SAR ADCs with bridge-DAC structure. The MCD algorithm replaces the gain factor calculation with simple missing-codes count that significantly reduces the calibration digital overhead. It also relieves the linearity requirement of the testing signal;...
This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900...
This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC...
This paper presents an ultra-low energy and compact Fast Fourier Transform (FFT) processor suitable for pervasive sensing systems. To achieve high energy efficiency and small area, we design area-efficient memory-based architecture and equip it with two proposed techniques: (i) spatiotemporally finegrained active leakage suppression for sub-threshold voltage (sub-VTH) combinational logic and (ii)...
A 1.02nW current reference is designed with only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation. Thirty-two measured chips from 5 corner wafers in 180nm CMOS technology show an untrimmed within-wafer spread (σ/μ) of 1.6% and across-corner wafer-to-wafer spread of ±4.7%. The measured average temperature coefficient is 282ppm/°C from −40°C to 120°C...
In this paper, we propose an ultra-low-voltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low Vt (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB...
This paper presents a LED driver IC based on a self-resonant Hybrid-Switched Capacitor Converter (H-SCC) operating in the MHz range. Capacitors and switches of the LED driver are integrated on-chip in a low-cost 5V 0.18μm bulk CMOS technology. The effective chip area is 7.5mm2. A conventional SMD output capacitor and a 6.4 mm2 150nH SMD air-core inductor are enough to operate the driver in a compact...
The latest extended-coverage (EC-GSM-IoT) and high-throughput (EGPRS2A) enhancements make GSM competitive to LTE-based cIoT standards such as NB-IoT with the advantage of global coverage today. This work introduces the first fully-integrated RF-SoC supporting the complete GSM standard family ranging from EC-GSM-IoT through EGPRS2A. The RF-SoC achieves −121.7 dBm receiver sensitivity and peak data...
The POWER9™ Processor in 14 nm SOI FinFET technology makes use of 7 different families of arrays. This paper gives an overview on advantages of different implementations, focusing on two key innovations introduced with this processor generation: Fast and low-latency write assist schemes for single-voltage performance arrays, as well as a new methodology, the synthesized soft arrays, to enable significant...
An energy harvester with a low startup voltage and wide input range is proposed mainly for solar power. In this work, neither any post-fabrication steps nor excessive external assistant components are required to startup the circuit with a low input voltage. Moreover, a voltage detector is proposed for widening the input voltage range. The proposed chip was fabricated by TSMC 0.18μm 1P6M mixed-signal...
Different from conventional multiphase switched-capacitor (SC) DC-DC converters, the proposed unsymmetrical parallel switched-capacitor (UP-SC) regulator provides more controllable input variables to increase available conversion ratios for improved load regulation. Even under higher conversion ratio numbers, the UP-SC regulator uses the fast searching optimum ratio (FSOR) technique to search the...
A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller...
This paper presents a fully integrated dc-dc converter with on-chip double galvanic isolation. The converter exploits only two dice both fabricated in a 0.35-μm BCD technology with a thick-oxide back-end for 5-kV galvanic isolation. It uses a novel architecture to transmit power across two isolation barriers, which are performed by integrated capacitors and transformers. LC coupling inherently enables...
The paper proposes a power supply unit to efficiently supply always-on or duty-cycled IoT loads which consumes in μW-range. This PS achieves the highest 93% and 99% current efficiencies at average output currents of 1μA and 100μA to date, respectively. This unit includes a voltage reference and oscillator to generate autonomously duty-cycled power delivery operation as low as a 30μ8 on-period. The...
A digitally controlled LDO in 14nm tri-gate CMOS powering an Atom™ core with embedded power gates enables per-core DVFS over a wide voltage-frequency range. The LDO demonstrates 99.6% peak current efficiency at 2.5A load current and provides a power density of 26.1 W/mm2. The multi-mode digital controller featuring non-linear mode and adaptive gain achieves <20ns settling time with a 100mV droop...
Future implantable devices demand ultra-low power consumption with self-calibration capability providing real-time processing of biomedical signals. This paper introduces an adaptive processing framework for highly accurate on-chip spike sorting processing by learning the signal model in the recorded neural data. The novel adaptive spike sorting processor employs dual thresholding detection, adaptive...
A class-AB and a class-J PAs for X-band phased array radar applications are presented. The class-AB fully-differential design features the cascade of a 8-bit PGA and a PA core, leading to a gain variation range of over 50 dB with a phase shift deviation of < 4° over a 25 dB attenuation range. The differential circuit shows 23 dB maximum gain, and 22 dBm saturated power at a PAE of 31%. Class-J...
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