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Due to a weak adhesion, the delamination occurred frequently in the interface between the epoxy compounds and lead that results in a performance failure normally. Several treatments, such as plasma and chemical modifications, have been developed and applied to enhance the bonding force in the interface of both materials. In this study, an anchor shape of the lead, as a mechanical locking microstructure,...
Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface...
10um × 100um TSV was prepared by deep reactive ion etching process. Barrier and seed layer were deposited by physical vapor deposition process and prior to Cu electroplating, Ni was electroplated on seed layer. Cu electroplating was optimized for solid TSV filling. To remove excessive Cu on field area, chemical mechanical polishing process is used in conventional TSV fabrication process. In this study,...
The interest in wearable electronics has been rapidly increasing due to the high demands for various wearable devices such as smart glasses and smart watches which satisfy the needs of today's customers. Future wearable devices will require fully flexible chip packaging performance and also maintain stable electrical performance under repeatedly bending environment. To meet these requirements, ultra-thin...
Among the technological developments pushed by the adoption of Through Silicon Vias and 3D Stacked IC technologies, wafer thinning on a temporary carrier has become a critical element in device processing over the past years. First generation of adhesive materials enabled the integration of the first devices at the expense of capping the thermal budget. Hence new generation materials are being explored...
Wafer Level Package (WLP) is a packaging technology focusing on IC packaging at wafer level instead of chip level. Conventional WLPs are designed for fan-in chip scale packaging but the shrinkage of pad pitch and size at the chip to package interface is much faster than the shrinkage at the package to board interface. Fan-Out Wafer Level Package (FO-WLP) is key technology to solve this problem. FO-WLP...
Fan-Out Wafer Level Packaging (FOWLP) has recently seen a tremendous growth in a broad span of application in telecommunications, automotive and other markets. Its versatility allows its continuous development to accommodate more and more types of components. In light of expanding the technology to include new family of sensors such as MEMS/NEMS, Bio-chips with Microfluidics, magneto-resistive devices...
This paper demonstrates a new class of inorganic-organic hybrid dielectric materials to address the requirements for high-temperature reliability of next-generation high-density, high-power packages and electronics in harsh environments for automotive applications. A major concern for reliability is the inadequate adhesion of metals with high-temperature polymers. Adhesion deteriorates further via...
In recent years, continuing enhancement of highly-functional electronic devices, such as mobile terminal devices, has significantly increased the volume and speed of data transmission. This made high-frequency communication for data transmission between electronic devices essential. Thus, device component suppliers must offer products with low transmission loss in high-frequency range. An insulating...
Over the past few years, temporary bonding has expanded together with the development of 3D stacked IC (SIC) technology. As maturity of the various processes has constantly improved, process yield and process impact on device performance have become key questions to answer. To further answer the refraining elements preventing a more massive technology adoption, in-line testing of the device throughout...
2.5D and 3D Integration technology using temporary bonding has become main stream in the semiconductor industry in recent years. However, thermal stability, low damage, and debonding at comparative low temperature are still areas of challenge. In this present study, a novel three-dimensional crosslinked polyurethane (3DPU) based on thermal reversible Diels-Alder chemistry, which can be used as temporary...
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