The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A layout technique via pulse quenching is tested in this paper. The limitation of layout technique is found by 3D device experiment. The new requirement of layout technique can be affirmed that layout technique via pulse quenching is more suitable in nMOS under 90nm technology.
The shallow junction is used in the PDSOI technology. Unfortunately, the standard diode model maybe not suit to this PN junction. A simulation model is proposed based on the PDSOI process. The additional influence of the voltage bias of the junction to the capacitance is considered in this model and then the model is well verified by the measured data.
A single photon avalanche diode (SPAD) device with deep P-well is proposed, which is protected by surrounding P-implantation layer, P buried layer and P+ buried layer. The P+ buried layer of this SPAD device has great help to enhance the uniformity of electric field in avalanche multiplication region. The primary contribution of the P buried layer is to improve the electric field at the edge. Therefore,...
With conventional Si-CMOS scaling approaching its fundamental limits and new materials such as III–V channel devices emerging, III–V/Si co-integrated technology has entered a pre-paradigm age for future heterogeneous integrated circuits and systems. Such an emerging technology platform opens new opportunities for innovative circuit designs in CMOS+X combinations where “X” can be, e.g., GaN/InGaAs...
With the decrease of the transistor feature size, aging phenomena is becoming one key factor affecting the performance of the circuit. Digital measure the performance degradation is one of critical problems in aging adaptive design technique. In this paper, we propose a delay amplified digital (DAD) aging sensor circuit which is combined aging principle with delay amplified circuit. Firstly, a reference...
This paper presents a process, voltage, and temperature (PVT)-independent constant-gm bias circuit, designed in 0.18µm CMOS technology. In this paper, the conventional precise off-chip resistor is replaced by a MOSFET operating in triode region with a novel bias circuit, which behaves like a PVT-independent resistor. Simulations show that the maximum gm variation across process corners is ±5.2%, and...
A closed-form drain current model for amorphous oxide semiconductor thin-film transistors is proposed in this paper. By adopting the effective charge density method and reformulating Lambert W function as two different exponential terms in different regions, both non-degenerate and degenerate conduction regimes are taken into account. Furthermore, an I–V model considering both the trapped and free...
As the device size downscales, hot carrier aging (HCA) scales up and remerges as a major challenge to the reliability of modern CMOS technologies. The conventional method for predicting the HCA device lifetime is based on a power law kinetics and critically depends on the accuracy of the time power exponent, n. In this work, we study how to extract the n accurately. It will be shown that the widely...
In this work, the SiGe nanowire pMOSFETs (NWT) for 7nm and beyond with Ge component varies from 20% to 90% are simulated by different methods including drift-diffusion (DD) vs Monte Carlo (MC) method for transport, and the Poisson-Schrödinger solver(PS) vs the density gradient (DG) approach for quantum effect. The impact of Ge component variation on the performance of pMOSFETs is also evaluated.
In this paper, a new steep-slope device concept of resistive-gate field-effect transistor (RG-FET), which is operated by electrically induced abrupt resistance change of gate stacks, is discussed in detail and experimentally optimized. The fabricated RG-FET demonstrates both an ultra-steep subthreshold slope of below 5mV/dec over almost 2 decades of drain current and a high on-current competitive...
A four-stage common-source (CS) amplifier is designed in a 65 nm CMOS process for the unlicensed D-band. Each stage bases on the technique of coupled transmission line (T-line) neutralization to achieve high performance. Transmission line is also used to provide inter stage impedance match together with transformers. T-junction network is used for input and output matching. With the proposed techniques,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.