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This paper proposes a sinusoidal signal generator algorithm and architecture for mixed-signal IC testing input as well as quadrature detection circuit applications. It can provide a rectangular waveform approximated to a single-tone signal with harmonics suppression; we can specify the harmonics to suppress using digital control. Its circuit consists of digital circuit, a 1-bit DA converter with an...
An efficient architecture of a 64-point FFT processor using two-dimensional algebraic integer (AI) encoding is presented. The advantage of two-dimensional AI encoding is that the hardware complexity for multiplication is reduced since a multiplication can be replaced by a few simple shifts and additions. The ROMless FFT processor, which replaces the ROM for twiddle factors with a twiddle factor generator...
A simple language for numeric computations on heterogeneous networks of programmable processors is described, in particular networks implemented in an ASIC, an FPGA or an SoC integrating hardwired processors and an FPGA. It relies on an infrastructure providing memory, communications, and various system services. The language supports the use of the multiple non-standard data types typically found...
In MEMS realization of high frequency ultrasonic array transducer, electrical impedance matching may become difficult for the reason of the miniaturization of the piezo-array elements. In this study, the electrical impedance of the array elements is estimated first by using KLM model, and then calculated by using finite elements method (FEM), in the case of a LiNbO3 based 30MHz array transducer. The...
In this work, a novel deep-impurity-level assisted tunneling technology with enhanced band to band tunneling (BTBT) probability is proposed and experimentally demonstrated. Through implanting deep level impurities in the tunnel junction, continuous deep level states can be introduced to facilitate the BTBT process for significant BTBT probability boosting. Compared with conventional tunnel diodes,...
A surface-potential-based compact model for the doped polysilicon (poly-Si) thin-film transistors (TFTs) is proposed in this paper. By develop in gap proximate explicit solutions of the surface potential from the Poisson's equation, we can express the drain current as explicit functions of applied voltages with using the charge sheet approach. Compared with the previous models, high accuracy and efficiency...
We proposed and fabricated amorphous indium-gallium-zinc-oxide thin-film transistors (IGZO TFTs) employing a novel organic-passivation layer (1-Methoxy-2-Propanol positive resist). The 1-Methoxy-2-Propanol passivated TFTs exhibit almost non-degraded electrical properties with carrier mobility, subthreshold swing of 5.9 cm2/Vs, 0.38 V/dec, respectively compared to the unpassivated TFTs. Besides, the...
In this paper, integrated circuit (IC) implementation of the modified sequential minimal optimization algorithm of supporter vector machine (SVM) is carried out to enable and speed up the learning process of the hardware system. This VLSI circuit system consists of three main operation modules and a control module. A concise and efficient examining module is designed to bring into full play of the...
We are facing many challenges for future nanoelectronic devices in the next two decades dealing with scaling, power consumption and computing performance. This paper presents the most promising solutions for the end of the roadmap in the More Moore and Beyond-CMOS fields, including innovative nanomaterials such as ultra-thin Si-Ge-III–V/OI, 2D layers (graphene, phosphorene, various transition-metal...
An ultra-low power frequency synthesizer based on a 28-nm CMOS dual-voltage controlled ring oscillator is presented. The technological dispersion and temperature effects are tackled thanks to a Delay locked loop (DLL) which sets a coarse tuning voltage. A back-gate fine tuning voltage is used to lock the oscillating signal on a pure reference with a Phase locked loop (PLL). The close-in intrinsically-poor...
Silicon interposer based 2.5D IC can realize heterogeneous integration and is effective to implement an electro-optical system. In this paper, we analyze the CPW structure transmission line on silicon interposer for high speed electro-optical system. The RDL-TSV-RDL transmission structure is used to reduce the resonance. An optimization method is proposed to improve the performance of the RDL-TSV-RDL...
This paper is an overview of low dielectric constant (low-k) materials developed for advanced interconnects and also presents recent innovative solutions for integration of ultra low-k dielectrics in ULSI devices. The innovative approaches include exploration of new candidate materials and technological solutions for interconnects integration in advanced technology nodes.
This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an excellent in-band phase noise of −90 dBc/Hz at 500 kHz offset with...
A compatible low-noise multi-phase voltage controlled oscillator is demonstrated in this paper. A compatible current steers are used to reduce the gain of VCO. The cascade structure of inverter is used to suppress the intrinsic noise and power supply noise. By increasing the output resistance of current steers with the cascade structure, the supply noise is suppressed. A modified inverter delay stage...
The electrical characteristics of Ti/p-SiGe contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. TiN was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/p-SiGe contact resistivity (ρc) increases, but its Schottky barrier height (SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using TiN/p-SiGe as a control sample,...
The application of carbon-nanotube to reduce interconnect delay is studied in this work, with the emphasis on how it can be used to reduce the inter-metal capacitance. By forming vertically aligned cylindrical pores assisted by vertically grown CNT, mechanically stable ultra-low-k interlayer dielectric with k-value down to 1.89 is experimentally demonstrated. Ways to integrate this process will other...
A new realization of a Voltage Controlled Oscillator (VCO) is introduced, and the description of its properties is provided. It is shown that this new realization offers several advantages in comparison with conventional VCOs and can be useful in certain design applications. Theoretical derivations and implementation are presented.
Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely...
This paper presents a novel fractional-N digital PLL structure with a digitally controlled phase interpolator (DPI) and a time-to-digital converter (TDC). In this structure, a short bit-width DPI and a short bit-width TDC are combined to achieve high phase resolution and low in-band phase noise. Moreover, since the DPI readily achieves 360° phase range and the TDC provides good linearity, no extra...
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