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Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks...
Even though much previous work explores adapting instruction queue (IQ) and reorder buffer (ROB) sizes to application requirements, traditional IQ/ROB optimizations may be prohibitive for resource-constrained embedded systems, due to the hardware/execution time overheads. We propose low overhead, phase-based instruction window optimization to dynamically vary IQ and ROB sizes for different execution...
Presently, almost all timing analyses and optimization tools are based on the strategy of setup and hold time constrained flip-flop timing model. However, this is a big mismatch with the timing characteristic of the real life flip-flops, which is so called flexible flip-flop timing, in which the clock-to-Q delay of every flip-flop may vary dynamically according to its setup and hold skews. This work...
This paper proposes a Mixed Integer Non-linearProgramming (MINLP) based optimization algorithm to designpower optimized pipelined ADC. For a given specification theproposed algorithm gives stage resolution and sampling capacitorper stage that minimizes the total power consumption. Closedform expressions of the power consumption of each stage werederived and used as objective function. Pipelined ADCs...
Increased power density and high temperatures are looming issues in many-core processors. Technology scaling trends, cooling limitations, and stringent application requirements make these issues rather difficult to handle. Consequently, it is imperative to design solutions that are effective and also scale well with increasing core counts. In this work, we present an application mapping framework...
Due to the increasing proliferation of computing systems in diverse application domains, the need for application-specific design of multicore/manycore processing platforms is paramount. In order to tailor processors for application-specific requirements, a multitude of processor design parameters need to be tuned accordingly. Tuning of processor design parameters involves rigorous and extensive design...
Lane-based Vector Processors (VPs) are highly scalable. However, they become less energy efficient as they scale for vector applications having insufficient data-level parallelism (DLP) to keep the extra computation lanes fully occupied. We present a scalable and yet flexible VP that is capable of dynamically deactivating some of its computing lanes in order to reduce static power with minimum performance...
Circuit legalization removes overlaps and keeps cell alignment with power rails whileminimizing total cell displacement. Legalization is applied not only after global placement, but also after incremental optimization steps like detailed placement, gate sizing, and buffer insertion. Applying full legalization after such incremental optimizations is too time-consuming. That is why physical synthesis...
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