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In this work, two quadratic formulations for incremental timing-driven placement are proposed. We include the delay model formulation into the quadratic function objective. Our timing-driven quadratic techniques perform path smoothing by optimizing the distance of neighbor critical pins and balance wire load capacitance in the critical nets by reducing their total quadratic length. In our incremental...
Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks...
In this work, we present a flow for the Incremental Timing-Driven Placement problem. Given a legal placement, the aim is to reduce the circuit's timing violations without changing significantly the cell density, subject to a maximum displacement constraint. Our flow consists of two core steps: useful clock skew optimization and critical path fine tuning. During useful clock skew optimization, sequential...
Most of recent placement algorithms are driven to HPWL minimization and routability improvement. Although timing-closure is one of the most essential aspect of the synthesis flow, few methods are currently targeting delay reduction by handling critical paths during global or detailed placement. In this work, we adapted a global placement algorithm to perform timing-aware incremental detailed placement...
Energy-efficient fast adders are needed in the design of battery-powered portable devices. Although many fast adder architectures exist, most of them require transistor-level optimizations that prevent their synthesis in a standard-cell flow. This paper presents two energy-efficient Add-One Carry-Select Adders (A1CSA and A1CSAH) suited for standard-cells synthesis. Synthesis results showed that the...
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