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We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved ION, +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (LG) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with...
We report a record setting low NMOS contact Rc of 2e−9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e−9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity...
The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on...
A novel physical unclonable function (PUF) that based on random telegraph signal noise (RTN) is proposed and studied in this work. Firstly, systematical experiments have been done in ultra-scaled devices with various gate stack structures. It is found for the first time that strong correlations between trap time constants and thermal activation energies universally exist in all devices, no matter...
3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint...
A new production ready compact model for future FinFETs is presented. This single unified model can model FinFETs with realistic fin shapes including rectangle, triangle, circle and any shape in between. New mobility models support Ge p-FinFETs and InGaAs n-FinFETs. A new quantum effects model enables accurate modeling of III–V FinFETs. Special attention is paid to shape agnostic short-channel effect...
We report the first experimental demonstration of Ge 3D CMOS circuits, based on the recessed fin structure. Both n-FinFETs and p-FinFETs with channel length (Lch) from 200 to 20 nm and fin width (WFin) from 60 to 10 nm are realized on a Ge-on-insulator (GeOI) substrate. The Ge FinFETs show superior gate electrostatic control over planar devices and sub-threshold slope (SS) as low as 93 and 73 mV/dec...
We demonstrate that fine-pitch TSV technology can be exploited to fabricate micro-inductors on high resistivity substrate, with record-high inductance per area and preserving their performance at GHz frequencies. We report an extensive experimental study on the effects of dimensional scaling and passive device density on RF performance of out-of-plane inductors exploiting W-based TSVs, with pitches...
Based on physically-extended methodology, measurements and simulations show that implementing high-mobility materials and particularly alloys, such as a SiGe buffer for mobility enhancement in a Ge channel, can result in a 115% increase in self heating in the N7 node, compared to standard Si FinFETs.
3D sub-system integration of logic and DRAM with TSV is desirable for wide memory bandwidth and reduced power for mobile applications. However, its manufacturing cost, along with testing and heat dissipation, remains to be outstanding issues. A new integration technology platform, InFO, is proposed to address it. In this paper, we compare three main 3D integration architectures: InFO_PoP, FC_PoP and...
A test circuit for studying Electromigration (EM) effects under realistic high frequency AC stress was implemented in a 32nm High-k Metal Gate (HKMG) process. Four different stress patterns (DC, pulsed DC, square AC and real AC) can be generated using on-chip circuits. Local heaters are used to raise the die temperature to >300°C for accelerated testing. Experiment results over 52.7 hours show...
This paper addresses automotive low power technologies in Internet of Things (IoT) societies, where the interaction among cloud information, real-time recognition and vehicle control is a key. High reliability and high performance with low power under the harsh operating conditions are strongly demanded for automotive microcontroller units (MCUs). Our developed embedded Flash (eFlash) and SRAM achieved...
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