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The semiconductor design industry has globalized and it is economical for the chip makers to get services from the different geographies in design, manufacturing and testing. Globalization raises the question of trust in an integrated circuit. It is for the every chip maker to ensure there is no malicious inclusion in the design, which is referred as Hardware Trojans. Malicious inclusion can occur...
This paper proposes a new sensor circuit to monitor on-chip frequency temperature changes in VLSI circuits. The proposed circuit exploits the temperature dependency of current/voltage of metal-oxide-semiconductor field effect transistor. The variation of current/voltage in the temperature sensor circuit with respect to temperature is subjected to a ring oscillator which provides the relative frequency...
With the advent of multi-core technologies, a significant amount of research has been directed towards running multiple applications concurrently and efficiently. This elevates work load on the network which leads to congestion and subsequently degrades the performance and increases the latency of the network. Table based methods can be used for handling congestion but these methods are not scalable...
Sense amplifiers are one of the important circuits in the CMOS memories as they have a greater impact on the access time and power dissipation of memory cells. The current-mode sense amplifiers have improved the access time as well as power dissipation to a large extent when compared to voltage-mode sense amplifiers, thus resulting in making the memories compatible with the high speed CMOS technologies...
QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.
In stress enabled technologies the drive strength of multi-fingered (MF) transistors varies with the number of fingers (NF) because of Layout Dependent Effect (LDE). This is an important issue because MF transistors are widely used in integrated circuits. In this paper, we investigate performance variability issues in basic analog building blocks, such as current mirrors, common source amplifiers,...
Temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a particle swarm optimization (PSO) based test pattern generation strategy has been proposed for BIST environment...
Register File (RF), Static Random Access Memory (SRAM) and Read Only Memory (ROM) arrays on SoCs comprise over 50% area and consumes substantial power on die. The On die ROM usage is increasing as there is an increased focus on IOTs, multi-core microprocessor for notebooks, 2-in-1s and mobile applications. Achieving high performance at low power specification need considerable innovation. Use of High...
Hardware IP design verification is performed using exhaustive random stimuli, while incorporating a coverage driven flow. On the other hand, system-on-chip (SoC) verification methodologies, sometimes, use a directed C-based verification approach to validate the functionality of the design. There is no significant randomization exercised in this process. Reuse of IP testbench components for SoC verification...
Traditional Mesh based Networks-on-Chips, are inherently slow due to hop-by-hop packet forwarding. The addition of Express Channels has emerged as a viable solution to reduce packet latency. However, there is a lack of application mapping methods, which can take into account the nature of the Express Channels. In this paper a constructive heuristic based approach has been proposed for application...
In this era of Internet of Things, wherein every ‘thing’ is integrated within the existing internet architecture, it becomes quite necessary that embedded computing systems process quickly, occupy less area and consume low power. This would enable them to work quickly with real time data and have a large shelf life. As such there is a need for development of optimized algorithms and their efficient...
High performance SOC contains considerable amount of SRAM memory occupying more than 60% of total SOC area. In CMOS process scaling down of feature size enables higher density and lower cost but high density array has significant impact on manufacturing yield and performance parameters of conventional 6T SRAM cell. In this paper we have presented an alternate area compact 5 transistor portless SRAM...
Increase in design complication for current and future era of microelectronics technologies and mechanisms used for data transmission leads to an increased sensitivity to bit-flip errors. As we know, multiple cores are built in a single system on chip (SoC) and to test that SoC, test vectors are transferred from automatic test equipment (ATE) via serial communication link. Now if there is a defect...
This work explores a methodology to optimize the layout of a electro-static discharge (ESD) structures for improving the performance of low voltage swing differential amplifier (LVDS). The parasitic capacitance of ESD structures are extracted. The role of our work is to optimize the parasitic capacitance in the I/O circuit while improving the ESD robustness. The work first compares impact of capacitance...
This paper describes a comparative study of sensitivity and non-linearity of conventional and bossed diaphragm piezoresistive pressure sensor along with a performance enhanced design. The proposed structures take into consideration corner compensation to avoid distortion of the mesa structure during fabrication of bossed diaphragm structure using wet bulk micromachining. Optimum piezoresistors locations...
This paper presents a strategy for optimization of scheduling for a set of real time control tasks using variable time periods. We assume non-preemptive scheduling of the tasks. The time period for each task is selected in such a way so that the performance of the system is optimized. An offline assignment of periods using branch and bound based methodology is proposed to find an optimal schedule...
The temperature sensor traditionally implemented using parasitic BJT in CMOS process is showing limitations in deep submicron technology node because of process variations. Since vertical PNP transistor in single n-well submicron process is prone to process variations, it impacts the accuracy of temperature sensor. Secondly, low voltage and low power specification of temperature sensor also goes against...
This paper continues to build on the dynamic current transient estimation method introduced in previous work. Our previously introduced method uses pre-characterized data from standard cells to estimate the total current transient of a path. This method eliminates the necessity of running resource intensive full-chip SPICE simulations to estimate the current transient of a path. Novel contributions...
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