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This paper presents novel capacitor less dynamic random access memory (DRAM) cells through band-gap engineered silicon-germanium (SiGe) junction less double gate field effect transistor (JL-DGFET) using two-dimensional commercial TCAD device simulator. The design window of capacitor less DRAM cell and its operations have been described. We observe hysteresis current-voltage characteristic and steep...
This work explores the new ESD (electrostatic discharge) protection design methodology for high speed off-chip communication ICs (Integrated Circuits). We propose novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition. Furthermore, we have discussed the ESD-I/O circuit interaction and improved the ESD circuit robustness...
This work explores a methodology to optimize the layout of a electro-static discharge (ESD) structures for improving the performance of low voltage swing differential amplifier (LVDS). The parasitic capacitance of ESD structures are extracted. The role of our work is to optimize the parasitic capacitance in the I/O circuit while improving the ESD robustness. The work first compares impact of capacitance...
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