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Digital multiplier and squarer circuits are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage...
High performance SOC contains considerable amount of SRAM memory occupying more than 60% of total SOC area. In CMOS process scaling down of feature size enables higher density and lower cost but high density array has significant impact on manufacturing yield and performance parameters of conventional 6T SRAM cell. In this paper we have presented an alternate area compact 5 transistor portless SRAM...
This work explores a methodology to optimize the layout of a electro-static discharge (ESD) structures for improving the performance of low voltage swing differential amplifier (LVDS). The parasitic capacitance of ESD structures are extracted. The role of our work is to optimize the parasitic capacitance in the I/O circuit while improving the ESD robustness. The work first compares impact of capacitance...
Detailed routing for multi terminal nets have been proposed in this paper for island style FPGA architectures. The demand of integrated circuits and their decreasing size keep the research on physical design automation alive. In the proposed technique, the detailed routing constraints for island style FPGAs are created in such a way that they can be represented as a set of Conjunctive Normal Form...
Voltage references are very essential components of analog VLSI circuits. A reference source is expected to remain constant against supply voltage, temperature and process parameter variations. The forward voltage drop across junction diode exhibits a negative temperature dependence of about 2mV/°C, which is compensated by a suitably scaled proportional to absolute temperature (PTAT) component to...
In this work, novel layouts of a 4:1 CMOS transmission gate multiplexer are presented. The proposed layouts are realized by following the design rules for 45 nm and 90 nm CMOS processes, with a supply voltage of 1.2 V. Both layouts are designed using two different routing strategies — using only one metal layer, and using two metal layers. The power dissipation and area are noted and compared in all...
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