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Cell stability with efficient operation are the two major concerns towards the design of SRAM bit cells in sub nanometer CMOS technologies. Supply scaling, intra-die parameter variations are some of the major factors governing the cell stability and controllability. This paper analyses the different stability criteria and the effect of various assist techniques in designing a SRAM cell for high speed...
In this paper we have proposed a novel Sense Amplifier (SA) design which is capable of predetermining the direction of offset in threshold voltage in the sensing transistors and which provides up to 24% more current differential by activating a path for current to flow in a device, parallel to the weaker transistor, thus compensating the inherent offset. Due to its self correcting capability, the...
The present work analyses 6T, 8T and 10T SRAM cell on the basis of the Data Retention Voltage (DRV) and its variation with temperature and sizing ratios. The reduction of power supply, for reduced power dissipation, is carried out in this paper. In this paper, DRV of a 6T, 8T and 10T SRAM was measured using Cadence tools at 45nm technology. The DRV of 6T SRAM cell simulated is compared with the DRV...
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