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Due to the globalization of the Integrated Circuit manufacturing industry and wide use of third party IP in the modern SoCs has opened the backdoor for Hardware Trojan insertion. The detection of Hardware Trojan is challenging because of its very rare activation mechanism and unpredictable change in the functionality of the system. This paper proposes a new hardware Trojan detection scheme using power...
In this paper we address the problem of generating large combinational circuits with good fan in and fanout distribution, high Rent factor and large number of reconvergent gates. Such circuits are in great demand in testing various circuit related algorithms as bench mark circuits or networks. Generation of such circuits is conjectured to be NP Hard problem and available tools are mostly proprietary...
The testing power is the biggest concern in modern VLSI chip testing as the testing power is very greater than the functional power which affects the reliability of the chip. In this paper low test power architecture is proposed which loads the pattern in one scan chain serially and the rest scan chains are loaded parallel by the serial scan chain one after the other. The proposed technique is very...
The semiconductor design industry has globalized and it is economical for the chip makers to get services from the different geographies in design, manufacturing and testing. Globalization raises the question of trust in an integrated circuit. It is for the every chip maker to ensure there is no malicious inclusion in the design, which is referred as Hardware Trojans. Malicious inclusion can occur...
Increase in design complication for current and future era of microelectronics technologies and mechanisms used for data transmission leads to an increased sensitivity to bit-flip errors. As we know, multiple cores are built in a single system on chip (SoC) and to test that SoC, test vectors are transferred from automatic test equipment (ATE) via serial communication link. Now if there is a defect...
In this paper, a timing driven placement engine which is based on the partition driven method is described. In the proposed method, the netlist are partitioned recursively to form smaller sub-circuits and to perform simulated annealing at a later stage when sub-circuits are relatively small. The proposed timing optimization approach is based on net weighting. We present three different approaches...
Traditionally BIST is most widely used testing methodology because of its online and at speed testing capability. The conventional BIST suffers from hardware overhead due to the presence of on-chip test blocks such as TPG, MISR, ROM and ORA. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the first flops of scan chains as TPG and...
Most of the chip-multiprocessors share a large sized last level cache(LLC) which is divided into multiple banks in NUCA based architectures. Recent study on LLC power consumption indicates that, LLC consumes principal amount of chip power. The LLC power consumption can be divided into two major parts: dynamic power and static power. Techniques have been proposed to reduce static power by powering...
Rapid growth in the cache sizes of Chip Multiprocessors (CMPs) to support high performance applications will lead to increase in wire-delays and unexpected access latencies. NUCA architectures help in managing the capacity and access time for such larger cache designs. Static NUCA (S-NUCA) has a fixed address mapping policy whereas dynamic NUCA (D-NUCA) allows blocks to relocate nearer to the processing...
Scan based Design for Testability structures are highly vulnerable to unauthorized access to the internal signals of a chip. This paper proposes a secure scan based design which prevents this unauthorized access without any compromise in the testability. The proposed secure architecture employs unique keys for each test vector. These unique keys are generated by a linear feedback shift register and...
To maintain the ever increasing demand for compaction as well as performance, 3D ICs were introduced. They have some additional advantages over their 2D counterparts in various aspects like heterogeneous integration, higher frequency, lesser interconnect length and increased bandwidth. Testing of core-based dies in 3D-SOCs poses many new challenges. This paper describes an automated post-bond core-based...
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