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In communication systems, the speech signal is affected by background noise which reduces perception of the received speech. In the near-end scenario, noise can't besuppressed as it is generated in real time (background) and it reaches human ear directly. Smart way is to enhance the speech samples with respect to varying background noise. This fact opens a space for developing an algorithm that would...
This project aims at verification and validation of IP core using software to automatically generate the test suite to cover all possible test cases of a processor IP core. A case study is being taken with an open source processor IP core CPU86 implemented in Very high speed integrated circuit Hardware Description Language (VHDL). The in-house developed Test Coverage Algorithm is used to generate...
This project presents the implementation of error reduction techniques in sample and hold circuit(S/H).S/H suffers from multiple errors such as droop, acquisition error, aperture jitter, etc. Mainly two hold mode errors that is charge injection and clock feedthrough. We are trying to mitigate these errors by using different design techniques. When a switch in the S/H turns on, the capacitor starts...
Due to the globalization of the Integrated Circuit manufacturing industry and wide use of third party IP in the modern SoCs has opened the backdoor for Hardware Trojan insertion. The detection of Hardware Trojan is challenging because of its very rare activation mechanism and unpredictable change in the functionality of the system. This paper proposes a new hardware Trojan detection scheme using power...
The testing power is the biggest concern in modern VLSI chip testing as the testing power is very greater than the functional power which affects the reliability of the chip. In this paper low test power architecture is proposed which loads the pattern in one scan chain serially and the rest scan chains are loaded parallel by the serial scan chain one after the other. The proposed technique is very...
Traditionally BIST is most widely used testing methodology because of its online and at speed testing capability. The conventional BIST suffers from hardware overhead due to the presence of on-chip test blocks such as TPG, MISR, ROM and ORA. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the first flops of scan chains as TPG and...
Hardware Trojan is a significant threat to the modern integrated circuits, Hardware Trojan is a modification in the circuit which can alter the functionality of the design. Due to the globalization of the Integrated Circuit manufacturing industry and the desperate use of third party IP in the system has increased the insertion of Hardware Trojan in the circuit day by day. This paper studies and experiments...
The testing power is the biggest concern in modern VLSI chip testing which affects the reliability of the chip. The testing power is very greater than the functional power because during the test mode almost all the part of the chip is active which elevates the testing power problem. In this paper a low test power BIST architecture is proposed which employs clock gating and scan staggering to reduce...
Hardware Trojan is a severe threat to the modern integrated circuits, which is posed by the IP business model and untrusted foundries. In most of the modern SoCs several block are licensed from third party IP vendor where the chances of Trojan insertion is high and Trojan can also be inserted in foundries which are all globalized generally untrusted. In this paper a new self-Trojan detection is proposed...
As the number of transistors in the chip has reached 2 billion, the power dissipation becomes the bottleneck in chip design, as power increases, the thermal dissipation also increases which in turn reduces the reliability of the chip and increases the packaging cost. Nowadays various power reduction techniques are adopted to target the power. Bus encoding technique is one among which reduces the dynamic...
Advances in VLSI technology has led to design of complex circuits, these complex circuits consumes high power. Several traditional methods such as power gating, clock gating, multi VT, variable VT etc., exists to reduce power dissipation. This paper studies Multi-VDD power reduction technique and implements the same for ISCAS89 S38417 benchmark circuit. From the experimental results, Multi VDD technique...
This paper discusses the development of an android based smart automated fluid dispensing and blending system. The developed system confines to juice dispensing and blending application used in food processing. The system operation is sliced into three layers of operations; user layer, decision making layer, and an action layer. The user layer consists of a touch screen based mobile application which...
Network Interface Module (NIM) is a front-end receiver block, which interfaces incoming signals from outside world in to the High Definition (HD) Radio Frequency (RF) receivers. In most of the cases, NIM receives only one type of signal and down converts RF in to Intermediate Frequency (IF). In modern receivers there could be a separate block for Tuner and demodulator or there could be a single integrated...
Built In Self-Test (BIST) is widely used test methodology for its testing cost, testing time and online testing capability. Traditional BIST suffers with high test hardware overhead which is due to presence of on-chip test blocks like TPG, analyzer, ROM etc. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the available scan chains...
BIST is one of the DFT techniques in which the test circuitry will be present along with the CUT. Different BIST architectures are proposed in order to reduce the area overhead, power overhead, test time and test costs. The STUMPS architecture is best suited for BIST environment in terms of area and power, but it requires external TPG and Compactor. This paper presents the modified low power STUMPS...
Structural test is the most efficient test to detect manufacturing defects. With ever increasing complexity of digital designs, structural test vectors alone are not sufficient to achieve the desired fault coverage. Functional test vectors are programs written with the design specifications in mind rather than manufacturing defects and this can help in testing some of the critical portions of design...
Design for Testability (DFT) based on scan and ATPG has been adopted as a reliable and broadly acceptable methodology that provides very high test coverage, but for large circuits, the growing test data volume causes a significant increase in test cost because of much longer test time and elevated tester memory requirements. Test compression or scan compression provides great reduction in test data...
In this paper, a technique to design the 8 bit continuous-time band-pass Sigma-Delta converters for 70 MHz is presented. The conversion from discrete-time (z-domain) loop-filter transfer function into continuous-time (s-domain) is done by using Impulse-invariant-transformation. The transconductor-capacitor filter is used to implement continuous-time loop-filter. A latched-type comparator and a TSPC...
Application of nanotechnology is very diverse, ranging from electronics, optics, photonics, communication, medicine, sensing, biotechnology and biomaterials, and to energy production. This emerging technology is capable of creating many new materials and devices in nanoscale with a vast range of above applications. It is well established that many materials with minimum dimensions on the nanoscale...
In this paper, a low-power, active-RC fifth order elliptic filter is designed with bandwidth of 40MHz. The filter designed is based on single-opamp resonator, which consumes less power compared to the standard filter design with less number of opamp. First filter is designed using MATLAB to get fifth order standard transfer function which is further used to calculate R and C values of the filter....
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