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Maximum-Likelihood (ML) decoding has been proven to fully exploit the corrective capabilities of a code, especially at very low Bit Error Rates (BER), avoiding pitfalls of approximate iterative decoding methods. However, there are huge barriers that inhibit the hardware development of realistic realizable Soft-Decision ML decoding algorithms for long block codes, due to the fact that this approach...
FinFET technology is pointed as the main candidate to replace CMOS bulk process in sub-22nm circuits. Predictive technology and design exploration help to understand major effects of variability sources and their impact on circuit performance and power consumption. In this sense, new design methodologies and new EDA tools must be able to deal with the new fabrication process and variability challenges...
High-Level Synthesis (HLS) has been a hot research topic for more than 30 years. During this long period, HLS has found many enthusiasts and also critics as well. Both of them have presented a lot of arguments for and against, which have helped HLS mature a lot. Modern HLS environments are not restricted to heuristic optimizations of abstract functional blocks (adders and multipliers) as early approaches...
This paper presents a transmitter for Network in Chip Stack (NiCS) high-speed serial point to point links using Through Silicon Vias. A low voltage swing capacitive coupling four level multi-bit transmitter is proposed. It is suitable for low resistive bulk substrates with a small coupling between signal channels. The transmitter has been implemented in 28nm CMOS technology and verified by circuit...
In this work, we investigate architectures that can provide the benefits of dedicated hardware implementations and the flexibility of software defined environments. We call this new approach a data defined environment, in which hardware and software scales together based on workload variability to provide state-of-the-art hardware energy-efficiency. An integrated architecture for rapidly implementing...
State-space modeling and analysis of a class of switched capacitor RF power amplifiers are introduced resulting in fast and accurate calculation of the output and supply-drawn power as well as of the voltage and current waveforms. Power derivation parameterized on component values and intermediate transformed impedances offers a tool for optimizing the switched capacitor RF power amplifier for maximum...
In this paper, an automatic gain control amplifier (AGC) is proposed. The proposed AGC aims at a large input and output swing with a rapid tracking capacity. Moreover, the proposed AGC has a quite simple structure, which is very important for High intensity focused ultrasound (HIFU) applications in which an array of identical circuits must be used. The designed circuit was simulated in a CMOS 0.35μm...
Secure implementations have two primary goals: being optimized (with respect to area, latency, power, or throughput) and secure against physical attacks, such as side channel analysis. Composite fields have been often proposed as a solution for the former problem, allowing implementations of the Advanced Encryption Standard targeted at resource constrained applications: additionally, they may also...
Co-designed Low Noise Amplifier (LNA) and dipole antenna in a RadioFrequency (RF) dedicated silicon technology, BÌCMOS9MW, are presented in this paper. The LNA is a two-stages cascode based on a SiGE:C 130 nm HBT optimized for maximum gain. The antenna is a dipole designed to match the LNA input impedance and maximize radiation diagram. Both are co-integrated directly on the silicon chip. The circuit...
In this paper a comprehensive analytical analysis is performed based on a new accurate electrical model of silicon photomultiplier (SiPM) detectors. The proposed circuit model allows to accurately reproduce the SiPM output time response regardless of the particular technology adopted for the fabrication process, and can also be profitably exploited to perform reliable circuit-level simulations. A...
Phase-Change Memory (PCM) is the most mature among back-end emerging memory technologies and a likely candidate for the next generation of non-volatile memories. This paper presents an innovative programming technique for the Low-Resistance State (LRS) in PCM. The technique consists of an appropriately shaped electrical pulse, capable of controlling the power provided to the memory cell in order to...
3D-MPSoCs integrate cores of several vendors and support different applications on a single die, providing large performance and cost reduction. 3D-technology presents many security challenges and offers new opportunities to implement protection countermeasures. 3D-NoCs can be explored to assist the overall security of the system. In this work, we propose a 3D-NoC hardware architecture able to protect...
Excessive test power dissipation results in over-testing, IR-drop, yield loss and even heat damage to the circuit under test (CUT). An efficient scan-shift power reduction scheme based on scan chain partitioning and test vector reordering is presented in this paper. After partitioning the scan chains into several segments equally, a heuristic ant colony optimization (ACO) algorithm is introduced to...
For the signal connections between two adjacent dies in 3D ICs, the RDL routing from IO pads to micro-bumps plays an important role In this paper, given a set of micro-bumps and a set of connecting nets on the upper and lower RDLs between two adjacent dies, based on the testing of single-layer routing[7], an efficient algorithm including initial matching-based micro-bump assignment and rip-up-and-reroute-based...
Good quality entropy sources are indispensable in most modern cryptographic protocols. Unfortunately, many currently deployed networked devices do not include them and may be vulnerable to Random Number Generator (RNG) attacks. Since most of these systems allow firmware upgrades and have serial communication facilities, the potential for retrofitting them with secure hardware-based entropy sources...
Several rectifier topologies dedicated for radio frequency (RF) energy harvesting have been proposed, but only a few have been reported to be able to harvest RF energy at low input power (LIP) levels. In this paper, we are focusing on fully gate cross-coupled (FGCC) rectifier structure, which gives good performance at LIP levels. In order to get an enough high output DC voltage, a 3-stage FGCC rectifier...
The design of a digital baseband for a low power wireless receiver in 65 nm CMOS is presented. It consists of decimation filtering, matched filters for data detection, and preamble based synchronization. The circuit was designed using low threshold devices in both low power (LP-LVT) and general-purpose (GP-LVT) domains. The fabricated circuits were functionally verified, and silicon measurements show...
Damage mitigation of critical infrastructures onset of an earthquake is a very important matter. In our work, we developed an earthquake warning and protection system through P-wave sensing that detects earliest onset of an earthquake before damaging ground shaking occurs. Our approach captures P-wave using redundant channels (dual sensors) and minimizes the possibilities of false triggers from harmless,...
This paper presents a study on different microwave structures used to integrate MEMS devices in printed circuit boards, and their effect on the linear phase response for switched delay lines applications. Three different prototypes were designed to realize the RF tracks required to integrate 0.5 mm pitch MEMS devices together with the meander delay lines. The structures includes: microstrip lines,...
Eye tracking is one of the potential techniques for the future human-computer interface. In order to promote an eye tracking device that take account of high performance, miniaturization, low cost and power consumption, we implemented the Purkinje eye tracking algorithm into a single FPGA chip with the SOPC (System on Programmable Chip) technology. The image capture, Adaboost algorithm based eye detection...
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