The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A serial interface module based on FPGA platform is designed for data communication between the operator console and Fire Control Computer. Various techniques adopted during the design and optimizations are presented in this paper. The module is developed using VHDL language and is integrated onto a SOC to achieve compact, stable and reliable communication. It supports different baud rates. In the...
Many network security applications such as Intrusion Detection System (IDS), Firewall and Data Loss Prevention System (DLPS) are based on deep packet inspection, in this packets header as well as payload of the packets are checked with predefined attack signature to identify whether it contains malicious traffic or not. To perform this checking different pattern matching methods are used by NIDS....
This paper is on FPGA based emulation which is one the approaches to perform pre-silicon SoC validation, accelerate system software development and to meet time-to-market demands. This paper presents a verification methodology of SoC and also deals with simplified implementation of complex clock designs in FPGA are presented, which needs to be skillfully handled to meet the said criteria. Each base...
In this paper we preset implementation of an optimized Sobel edge detection algorithm on FPGA. The optimized gradient based edge detection method reduces the area up to 48.76% compared to existing gradient calculation unit, and also reduces propagation delay up to 51% compared to the area optimized architecture. The entire project is implemented on Spatran-3E FPGA board. VGA interface is used to display...
The paper presents the details of development of the fiber optic link that will be used to interconnect the various analog signals. Speciality of the link is that the analog signal of frequency up to 1 kHz is transmitted through digital technology. In order to resolve the problem of DC balance and clock/data recovery during the fiber optic data transmission, paper gives a simple and practical solution...
As technology is growing wireless communication is also rapidly growing and finding potential application in industries. Development of highly efficient DDC architecture is very important since with rapid technology growth need for complex services are increasing demanding for high data rate transmission and high speed multimedia services. In DDC system two major operations are carried out. First...
Cascaded Integrator Comb (CIC) structure is used extensively in the design of a decimation filter. This paper analyses the existing design of decimation filter and proposes a new design with reduced hardware requirements. The designs are modelled using VHDL, simulated using ISim and implemented in Spartan 3E FPGA. The synthesis report shows the reduction in number of I/O bits.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.