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In this study, special STT-RAM were designed, built and tested, allowing to read and write at similar voltages. This is achieved by maximizing the Spin-Transfer-Torque (STT) efficiency on the storage layer magnetization during write and minimizing it during read. In order to achieve this STT tuning, double barrier magnetic tunnel junctions were prepared wherein the storage layer is sandwiched between...
In this paper, an embedded 2T SONOS nonvolatile memory structure has been proposed for an embedded NVM cell in 90nm standard HVCMOS process. This nonvolatile cell can be fabricated by several steps such as ONO formation, cell junction implant, removal ONO films, those steps are non-critical processes and masks. The cell is operated by CHEI programming and BTBT-HHI erasing. The cell has been confirmed...
Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by...
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