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Provides a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
Today's embedded systems require multiple functions such as real-time control and information technology and integrating these functions on a multi-core processor is one effective solution. However, this increases overhead as it is necessary to partition resources in this approach to protect them. We developed hardware support called ExVisor/XVS to reduce the overhead of partitioning resources to...
In this research, a high performance computing weather forecasting application GRAPES has been tuned onto a functional unit (FU) array based architecture. Software and hardware approaches are specifically employed to increase the data locality and data reuse to accelerate the stencil computation in GRAPES. The simulation results indicate that we can achieve a per-core average IPC of 12.3 within a...
Processor performance and functional improvement has been driven by innovations in various areas, such as architecture, circuit, device, and software, but we are now facing or will face hard challenges, such as power consumption and process technology. What would the next step be in processor evolution? This panel will discuss with experts from HPC, server and embedded area what the requirements of...
Super Resolution image processing (SR) is a heavy task for a today's mid-range Xeon server. To accelerate SR, we utilize a server system with manycore coprocessor, Intel Xeon Phi coprocessor. Function offload model is a usual execution model for those systems. However it is difficult for SR to increase utilization of both host processors and coprocessors by the model. We propose a virtual pipeline...
A processor having a power management unit (PMU) and an 8-bit CPU including flip-flops with shadow memories is fabricated by 0.5-μm Si and 0.8-μm c-axis-aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO) technology. The shadow memories hold data without power supply utilizing low off-state current of CAAC-IGZO FETs. A break-even time (BET) of 4.9μs has been obtained. Good scalability of the processor...
This paper proposes a novel cache replacement policy named a flexible insertion policy (FLEXII) for dynamic cache resizing mechanisms. FLEXII can reduce the number of dead-an-jill blocks, which are never reused in a cache memory, and help the mechanisms further reduce the energy consumption. The experimental results indicate that FLEXII can reduce the energy consumption of the cache memory by up to...
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
The goal of this conference is, as always, to be part of the premier conference series on microprocessor architecture and technology. This rapidly growing field regularly and aggressively produces innovative ideas and products that enable a transformation of the world around us day by day. Starting as an IEICE conference in 1998, today the COOL Chips conference series has become an internationally...
COOL Chips XVI, the 16th IEEE Symposium on Low-Power and High-Speed Chips features 7 keynote and invited talks, and 12 technical papers. The keynote and invited talks cover a wide variety of topics such as low power technologies, low-power/high-performance processor designs, and cool applications co-designed with low-power hardware platforms. For organizing the technical sessions, the Program Committee...
Network-on-Chips (NoCs) with wireless inductive coupling have been utilized in real heterogeneous multicore systems. Although the inductive-coupling itself is energy-efficient (e.g., 0.14pJ per bit [1]), inductors continuously consume a certain amount of power, regardless of packet transfers. That is, inductors waste significant power especially when the utilization of vertical links (i.e., inductors)...
A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multi-core accelerators improves computational energy efficiency by proper task assignment and massive parallel computing. The stacked chips interconnect through a scalable 3D Network on Chip (NoC). By simply changing the number of stacked accelerator chips, processor...
COOL Chips XVI, an international symposium that provides the latest developments on low-power and high-speed chips. This year we present an exciting program that includes four keynote speeches, three invited talks, and two instructive special sessions.
Provides a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Array (FPGA), nonetheless the performance gap between FPGA and ASIC has remain very wide mainly due the programming overhead of FPGA. Three-Dimensional (3D) integration is a promising technology to reduce wire lengths. Through Silicon Vias (TSV) provide electrical connectivity between multiple...
Currently few mobile applications exploit the power- and performance capabilities of multi-core architectures. As the number of cores increases, the challenges become more pressing. We picked three challenges: application parallelization, performance-predictability/portability and power control for mobile devices. We tackled the challenges with our auto-parallelizing compiler and operating system...
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