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This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Torque Transfer-Magnetic Tunnelling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next,...
Fluctuations have recently been recognized as powerful resources that can be exploited to drive computations, but their use has mostly been limited to logic circuits. This paper goes further and explores a more general framework, in which computation is modeled as a process with a multitude of fluctuating tokens that interact with each other directly or via stigmergy. For the implementation of these...
The recent invention of magnetoresistive bipolar spin-transistors makes possible the creation of new spintronic logic families. Here we propose the first logic family exploiting these spin-transistors, extending emitter-coupled logic (ECL) to achieve a greater range of basis logic functions. By placing the wire from the output stage of ECL logic elements near spin-transistors in other parts of a circuit,...
The memristor is one among the most promising emerging technologies for enabling a new generation of Non Volatile Memories. The memristor operates faster than a Phase Change Memory (PCRAM) and has a simpler structure than a magnetic memory (MRAM), while making possible the design of cross-point structures in crossbars at very high density. The presence of sneak path currents however causes an increase...
Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density...
Graphene is an emerging nano-material that has garnered immense research interest due to its exotic electrical properties. It is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper, we present...
As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a statistical model of Negative Bias Temperature Instability (NBTI) tailored for FinFET SRAM Arrays. The model build upon an extension of the reaction-diffusion...
In this work we present an ultra low energy, ‘on-sensor’ image processing architecture, based on cellular network of spin based neurons. The ‘neuron’ constitutes of a lateral spin valve (LSV) with multiple input magnets, connected to an output magnet, using metal channels. The low resistance, magneto-metallic neurons operate at a small terminal voltage of ∼20mV, while performing analog computation...
This work proposes two learning architectures based on memristive nanodevices. First, we present an unsupervised architecture that is capable of discerning characteristic features in unlabeled inputs. The memristive nanodevices are used as synapses and learn thanks to simple voltage pulses which implement a simplified “Spike Timing Dependent Plasticity” rule. With system simulation, the efficiency...
As the efficiency of neuromorphic systems improves, biologically-inspired learning techniques are becoming more and more appealing for various computing applications, ranging from pattern and character recognition to general purpose reconfigurable logic. Due to their functional similarities to synapses in the brain, memristors are becoming a key element in the hardware realization of Hebbian Learning...
As feature-size scaling and “Moore's Law” in integrated CMOS circuits further slows down, attention is shifting to computing by non-von Neumann and non-Boolean computing models. Reservoir computing (RC) is a new computing paradigm that allows to harness the intrinsic dynamics of a “reservoir” to perform useful computations. The reservoir, or compute core, must only provide sufficiently rich dynamics...
We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase...
“Normally off, instantly on” applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off...
This paper presents a HSPICE macromodel of a phase change memory (PCM) cell. The model simulates not only the resistance change by phase (as corresponding to the two states, amorphous and crystalline), but also the temperature profile, the crystalline fraction during the programming and the drift behavior in resistance and threshold voltage. The proposed macromodel (consisting of two models) generates...
Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in integrated circuits (ICs) design for advanced process technology nodes. This paper proposes a Markovian framework to asses and predict the IC lifetime by taking into account the joint effects of process, environmental, and temporal variations. By allowing the performance boundary to vary in time such...
The performance of a method for robustly writing conductive states into resistive switches is analyzed. The focus is set on the variability of the conductance distribution which has a strong impact on the signal margin and the robustness of the circuit performance. In order to be able to capture cycle-to-cycle as well as device-to-device variability an existing device model for ECM cells was extended...
Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/design co-optimization approach for designing logic tiles for double-gate silicon nanowire field effect transistors (DG-SiNWFET) technology. A compact...
Logical irreversibility will be an important factor to consider in nanocircuits, which reach gate density and operating frequency in the regime of the recently experimentally proven Landauer's Principle. The resulting heat density will limit the performance of classical digital circuits implemented with nanoscale components, when other heat factors are minimized, as in the predicted highly energy-efficient...
With the high complexity of current digital circuits, the use of gate-level models during the design process is mandatory. For standard CMOS technologies, designers assemble standard cells for which the gate-level model is provided by the founderies. For a given technology, the temporal parameters (such as propagation delays) are constants that can be extracted from experimental measurements. For...
This paper describes the circuit design of a polarity controllable triple-mode amplifier based on ambipolar graphene field-effect transistors for analog, mixed-signal, and radio frequency (AMS/RF) applications. We describe how such polarity controllable circuits can greatly simplify circuits for applications such as phase shift keying and phase detection in the AMS/RF space, with the potential to...
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