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In this paper an image correlation algorithm is implemented on FPGA architecture for assisted movements of visually impaired persons or automotive driving systems. Taking into account the limitations of FPGA devices and the special requirements of the correlation based image matching algorithm a semi-parallel approach is proposed. This provides an optimal tradeoff between area and speed of the implemented...
Vision chips are natural candidates for being among the first areas that are able to utilize the emerging 3D integration possibilities. In some 2D vision chip architechtures there are pixel level AD and/or DA converters that are used for various purposes. This article covers the challenges and needs when targeting a megapixel architechture within a 1cm2 chip area. The Through-Silicon-Vias (TSVs) on...
Cellular Neural/Nonlinear Networks (CNNs) constitute an effective approach for studying complex phenomena like autowaves, spiral waves or pattern formation either by providing a computationally efficient environment for numerical simulations or by allowing the possibility of hardware emulators of the system under study. In this work, we focus on a CNN made of memristor-based cells, namely a Memristive...
Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we address a key issue in pattern matching and classification...
Embedded sensor-processor system is being developed for on-board UAV (Unmanned Aerial Vehicle) safety applications. The role of the device is to detect intruder airplanes which are on or close to collision course. Due to weight, power, size, and cost requirements, the visual approach leads to feasible solution only. In our design, 5 cameras are applied to collect visual data from a large field of...
This paper describes a real-time application programmed into Wi-FLIP, a wireless smart camera resulting from the integration of FLIP-Q, a prototype mixed-signal focal-plane array processor, and Imote2, a commercial WSN platform. The application consists in scanning the whole scene by sequentially analyzing small regions. Within each region, motion is detected by background subtraction. Subsequently,...
Presented in this paper is a demonstration system that uses a low-power SCAMP-5 256×256 vision-chip to locate and count multiple objects moving at high speed along arbitrary trajectories. The hardware consists of a SCAMP-5 IC, its power supply system and a Xilinx Spartan3 controller. At 100,000fps, the SCAMP-5 chip can locate and readout the coordinates of a single closed-shaped object amongst clutter...
Complex dynamical systems establish offer entirely new possibilities to the development of groundbreaking data processing methods. In the domains of image and video processing, locally coupled cellular array computers, based on Cellular Nonlinear Networks (CNN), accelerate the computation of large amounts of data in real-time, due to their inherent concept of massive parallelism. Current VLSI implementations...
We describe a pilot project for the use of GPUs in a real-time triggering application in the early trigger stages at the CERN NA62 experiment, and the results of the first field tests together with a prototype data acquisition (DAQ) system. This pilot project within NA62 aims at integrating GPUs into the central L0 trigger processor, and also to use them as fast online processors for computing trigger...
An FPGA implementation of a fine grain generalpurpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 × 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale...
This paper describes the of a 90 nm CMOS sub-THz detector array ASIC. The sub-THz detector array is an integrated system composed of silicon field effect plasma wave sensors, various integrated antennas, pre-amplifiers, ADCs, and digital domain lock-in amplifier detector. The peak responsivity is found 185 kV/W@365 GHz and 52 kV/W@470 GHz and at the detectivity maximum NEP ∼ 20 pW/Hz−1.
The CNN (Cellular Neural Network) is a powerful image processing architecture whose hardware implementation is extremely fast. The lack of such hardware device in a development process can be substituted by using an efficient simulator implementation. Commercially available graphics cards with high computing capabilities make this simulator feasible. The aim of this work is to present a GPU based...
A feasibility study of VLSI hardware implementation of support vector domain description (SVDD) has been done in this work. The on-chip learning operation of SVDD algorithm was implemented by an analog Gaussian-cell array. By using a compact analog Gaussian-generation circuit, the center, height and width of the generated Gaussian kernel function feature can be programmed. Based on this Gaussian-generation...
A low-power demonstration system using a SCAMP-3 vision chip to track and count multiple objects with unpredictable trajectories is presented. The system can track as many discrete objects that can fit into its visual field. The compact, self-contained hardware consists of a battery, an ARM Cortex-M3 coprocessor, and the sensor/processor array device. The tracking algorithm is performed entirely by...
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