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This paper describes a new physical analysis technique based on changing the number of the AES rounds. It is an extension of the already known Round Reduction Analysis techniques. Round Modification Analysis is a specific algorithm modification attack. However, the cryptanalysis of the obtained erroneous ciphertexts resorts to the differentiation techniques used by Differential Fault Analysis. Faults...
Physical attacks focus on extracting information from internal parts of IC's. One way to achieve this is by means of connecting probes to wires, so that the content of internal buses and registers can be revealed. Protection against this type of attacks exists, but usually is bulky and expensive, e.g. the shielding of secured areas. This paper presents a novel in-circuit countermeasure that is cheap...
Field Programmable Gate Arrays (FPGAs) need built-in security not only to prevent reverse engineering, but also to prevent hacking and cloning while reconfiguring or partially reconfiguring the devices. To counter such threats, methodologies for preventing IC piracy have been developed that require a unique signature key for every fabricated chip. Physically Unclonable Functions (PUFs) can be used...
The emergence and proliferation of Smart Cards and other security-centric technologies require ongoing advancement in secure-IC design. We propose advanced IC protection from Differential Power Analysis attack though a hybrid-logic style based on Complementary Pass-transistor and Dynamic and Differential Logic (DDL) in conjunction with a synthesis methodology based on Reduced Ordered Binary Decision...
Hardware Trojan (HT) is a growing concern for the semiconductor industry. As a non-invasive and inexpensive approach, side-channel analysis methods based on signatures such as power, current, or circuit delay are widely used for HT detection. However, the effectiveness of these methods is greatly challenged by the ever-increasing process variation (PV) effects with technology scaling. In this work,...
The problem of malicious inclusions in hardware is an emerging threat, and detecting them is a difficult challenge. In this research, we enhance an existing method for creating assertion-based dynamic checkers, and demonstrate how behavioral security requirements can be derived from a processor's architectural specification, then converted into security checkers that are part of the processor's design...
Security assurance is a rapidly evolving but well understood discipline in the software industry. Many firms have adopted the Security Development Lifecycle as a process to identify and fix vulnerabilities in their products before they are released. To do this, they rely on sound software security practices, tools and precise technical information available through a vast collection of publicly known...
This work introduces a novel, automated methodology for performing functional analysis of integrated circuits (ICs), such as microcontrollers and smart cards. By selectively executing code on a given chip, the resulting optical emission images yield critical information about the chip's functional layout. Automation of the code-generation allows us to generate and process hundreds of test cases that...
Due to the propagation of the glitches in combinational circuits side-channel leakage of the masked S-boxes realized in hardware is a known issue. Our contribution in this paper is to adopt a masked AES S-box circuit according to the FPGA resources in order to avoid the glitches. Our design is suitable for the 5, 6, and 7 FPGA series of Xilinx although our practical investigations are performed using...
Side channel attacks exploit physical imperfections of hardware to circumvent security features achieved by mathematically secure protocols and algorithms. This is achieved by monitoring physical quantities, usually power consumption or electromagnetic radiation, which contain information about the secret data. As a countermeasure, several circuit styles have been proposed for designing side-channel...
We demonstrate the efficacy and associated costs of three reliability enhancing techniques for bi-stable PUF designs (SRAM and sense amplifier-based) — directed accelerated aging, multiple evaluations, and activation control. Measured results from a 65nm bulk CMOS full custom PUF testchip demonstrate that these technique are able to reduce the percentage of unreliable bits by up to 40%, 83%, and 71%...
Since their introduction in 1996, the effectiveness of side channel attacks has been highly improved and many countermeasures have been invalidated. A very common countermeasure consists in randomizing sensitive variables of algorithms by masking techniques. In this paper, we propose a new way to apply this strategy to secure hardware implementations of block ciphers. The main advantage of the proposed...
Security mechanisms such as encryption, authentication and feature activation depend on the integrity of embedded secret keys. The mechanism by which these ‘digital secrets’ are stored within Integrated Circuits (ICs) is changing from EPROMs and/or fuse technology to Physical Unclonable Functions (PUFs). PUFs leverage the naturally occurring manufacturing variations within each IC to produce repeatedly...
A new sensor of Focused Ion Beam (FIB) attacks on security sensitive ICs is presented. The function is based on the FIB navigation process mandatory for FIB attacks, which covers a wide chip area, but deposits only a low charge density. Detecting this very low charge with extremely sensitive local charge sensors allows a loose distribution over the IC. The performance requirements of the charge sensors...
In this paper we present improvements of the algebraic side-channel analysis of the Advanced Encryption Standard (AES) proposed in [1]. In particular, we optimize the algebraic representation of AES and the algebraic representation of the obtained side-channel information in order to speed up the attack and increase the success rate. We study the performance of our improvements in both known and unknown...
Computer aided design (CAD) tools are fundamental for ensuring a short time-to-market in nowadays chip design. However, while CAD tools support the development of efficient designs, they fail to support the designer with regard to side-channel security. In order to better assist the designer, we propose the AMASIVE (Adaptable Modular Autonomous SIde-Channel Vulnerability Evaluator) framework that...
Cloning, theft of service and tampering have become serious threats on the revenue and reputation of hardware vendors. To protect their products against these attacks hardware security, based on cryptographic primitives using keys, can be used. These keys are usually stored somewhere in the hardware, so the strength of the security depends on the effort required from attackers to compromise them....
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
In this contribution, we present Complementary Index-Based Syndrome coding (C-IBS), a new and flexible fuzzy embedder for Physical Unclonable Functions (PUFs). C-IBS applies IBS several times to the same group of PUF outputs. The additional parameter permits an application specific tradeoff between error correction capability and implementation complexity. We demonstrate the flexibility of C-IBS by...
The horizontal dissemination of the chip fabrication industry has raised new concerns over Integrated Circuit (IC) Trust, in particular, the threat of malicious functionality, i.e., a Hardware Trojan, that is added by an adversary to an IC. In this paper, we propose the use of a high-precision, low-overhead embedded test structure for measuring path delays to detect the delay anomalies introduced...
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