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The complexity of ion implant applications in IC fabrication has grown significantly since becoming the preferred process for doping semiconductors. Aggressive device scaling over the last decade raised unique challenges. This resulted in the invention of novel implant applications to address device scaling driven issues and the development of new generations of ion implanters. These newly developed...
The 12th International Workshop on Junction Technology (IWJT-2012) is scheduled to be held on May 14-15, 2012 in Shanghai, China. Thanks to the great support of the engineers and scientists in this field, the workshop has been recognized in the world as one of the key technical meetings in the field of junction technology and has been referenced in numbers of papers. The IWJT-2012 has accepted 57...
Contact resistance (Rc) contributes over 65% of the total source to drain series resistance in < 32 nm CMOS technologies. In this work, reduction of Rc is achieved by lowering the SBH through the incorporation of new materials into NiPtSi. The impact of implanted elemental species as well as alloyed low work function metals is discussed. As diffusion and subsequent interface composition is...
Band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is investigated by x-ray photoelectron spectroscopy (XPS). The p-type Schottky barrier height (p-SBH) is found to increase with thicker HfO2 thickness. Since considering only the metal/dielectric interface cannot explain this phenomenon, band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is demonstrated based on band alignment...
This paper explores two low temperature technological developments related to future n-MOSFETs using III–V semiconductors as channel materials. (1). It was found that Yb-GaAs Schottky contact with RTA at 500°C for 30s has good rectifying characteristics, low effective electron barrier height, low sheet resistivity, atomically sharp junction with GaAs. These properties are suitable for source/drain...
Much attention has been paid to the site-specific scanning spreading resistance microscopy (SSRM) for visualizing impurity-diffusion layers because of its capability of failure analysis as well as analyzing scaled LSI devices. We report applications of the site-specific SSRM to failure analysis in LSI production lines for the first time. SSRM is shown to be capable of observing no implantation areas...
A physical-based and explicit calculation of surface potential for fully-depleted polysilicon thin-film transistors is proposed in this paper. For fully-depleted devices, not only the surface potential in the channel, but also the potential at the back surface are solved analytically. An exponential density of defect states is taken into account. The proposed scheme to calculate the surface potential...
Based on the surface potential calculation by the 1-D poisson's equation, the grain boundary barrier height at channel surface is derived accurately assuming an exponential density of trap states (DOS) within the energy gap. The threshold voltage is defined as the gate voltage when the free charge density is equal to the trapped charge density at the surface of channel, corresponding to the depleted...
Varied Lateral Thickness (VLT) technology is a novel voltage-sustaining technology which has been developed recently. This paper focuses on the static and dynamic operation performance of SOI LDMOS using the VLT technology. Firstly, the VLT LDMOS is optimized by using the TCAD tool to maximize the off-state breakdown voltage. The results show that the drift doping concentration and the breakdown voltage...
In this paper, we investigate the important device characteristics of block oxide (BO) MOSFETs (bMOS), which are the BO length (Lbo) and the height (Hbo). According to the simulation results, the variation of Lbo and Hbo strongly affects the device characteristics, such as the sub-threshold swing, threshold voltage, on-state drain current (Ion), and the off-state drain current (Ioff). This is because...
2D distribution of depth profiling of impurities and their activity/non-activity are very important for development of process technology for nano-scale 3D devices. Si Fin structures doped with Boron (B) were evaluated by soft X-ray photoelectron spectroscopy (SXPES) and a feasibility of detecting the difference were demonstrated between the chemical bonding states as well as concentrations of B on...
This work presents two-dimensional (2-D) self-consistent Monte Carlo (MC) simulation of the properties and physics underlying carrier transport through GexSi1−x/Si heterojunctions. Carrier transport in the two different semiconductor materials is included simultaneously and carrier crossing the heterojunction interface is modeled by the thermionic emission. The Si full-band structure obtained from...
Ultra shallow junction with high activation is necessary to reduce source/drain resistance and enable continued device scaling. The adoption of non-planar device architectures also presents new doping profile engineering challenges due to the 3D nature of the channel and source/drain regions. Advanced doping technologies are emerging to meet the new USJ and profile engineering challenge. Due to the...
Today, most of the state-of-the-art USJs fabrication processes involve the formation of an amorphous surface layer before or during the dopant implant step. In this paper, we present a review of some recent experimental studies on the Boron precipitation and trapping in pre-amorphised USJs. These studies suggest that the physical mechanism governing the Boron trapping mainly depends on the Boron concentration...
We compared BF2, In, Ga, C+Ga and In+BF2 dopant species for nMOS HALO at 22nm node for planar bulk & PD-SOI or for FD-SOI ground plane back-gate doping which require steep retrograde dopant profile and good dopant activation using a 1200°C Flash + 900°C 10 sec RTA anneal sequence. The best results were with the C+Ga co-implant realizing a steep surface dopant profile and dopant activation in the...
Beyond 65nm node, pattern loading effect (PLE) in conventional RTP (front-side heating) has been emerged as a major yield killer. Different pattern and deposited film property strongly influence thermal absorption and emission at the integration stage of the spike anneal (e.g., STI, poly, and nitride spacers) lead to significant temperature differences across each die. Several methods for reducing...
Annealing of 3D architectures is one of the major challenges for current and next generation devices for various applications ranging from sensors, microprocessors or high density memories. One of the most promising solutions is Laser Thermal Annealing (LTA), an ultrafast and low thermal budget process already adopted in production for passivation of BackSide Illuminated CMOS Imaging Sensors (CIS)...
We have developed a high-power-density micro-thermal-plasma-jet (μ-TPJ) to achieve ultra-rapid thermal annealing. Microsecond annealing was performed by μ-TPJ irradiation to an As-implanted Si wafer to form an ultra-shallow junction (USJ). The μ-TPJ could anneal the Si wafer surface at a temperature as high as 920 K for 340 µs. By reducing the annealing duration (ta) from 1.2 ms to 340 µs, the sheet...
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