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The paper presents an objective to build generic analog devices which can not only be customized to desire specification by the user in a field programmable manner but can also produce fine trimming ability in the designs using on-chip, non-volatile, real time/indirectly programmable floating-gate transistors. The basic analog building blocks based on above dimension are field programmable op-amp...
The need for building systems that are secure by design is being driven by increasing number of security threats and the cost due to system compromise. With the pervasive deployment of information technology in our lives the situation today is such that everything is a computing device — it can process, store and is networked for communication. There is increasing interdependence of all these networked...
There have been many exciting advances in field-programmable technology since the first FPT Conference took place ten years ago. Just as the FPT Conference has established itself as a major event, field-programmable technology has become widely adopted for many electronic devices and computing systems. This talk reviews the progress of field-programmable technology made in the past decades, and proposes...
In many application domains, data are represented using large graphs involving millions of vertices and edges. Graph analysis algorithms, such as finding short paths and isomorphic subgraphs, are largely dominated by memory latency. Large cluster-based computing platforms can process graphs efficiently if the graph data can be partitioned, and on a smaller scale partitioning can be used to allocate...
In this paper we present a simulation framework for rapid testing of custom hardware peripherals designed to be incorporated in a System on Chip (SoC) architecture. The QEMU processor emulator is extended to allow attaching a simulation environment to the system bus, such that simulation can perform bus transactions, and interact with the emulated processor. We demonstrate multiple levels of simulation...
A method for generating high speed FIR filters with low complexity for FPGAs is presented. The realization is split into two parts. First, an adder graph is obtained using an existing multiple constant multiplication (MCM) algorithm. This adder graph describes the required multiplier block of the FIR filter using only additions/subtractions and shifts. Secondly, a novel FPGA-specific combined schedule...
In this work, we explore heterogeneous computing hardware, including CPUs, GPUs and FPGAs, for scientific computing. We study system metrics such as throughput, energy efficiency and temperature, and formulate the problem of workload allocation among computing hardware in mathematical models with regards to the three metrics. The workload allocation approach is evaluated using Linpack on a hardware...
Modern embedded systems incorporate multiple applications that run on the same execution platform. However, due to limited resources and other constraints, not all the combinations of applications may run concurrently. This paper tackles the problem of determining which combinations of applications can run on a given hardware architecture without violating given constraints, thus creating feasible...
Least Squares Support Vector Machines(LS-SVM), which is an efficient supervised learning tool, has been widely applied to real-time on-line data processing in many fields. However, the on-line training of LS-SVM always suffers from huge computation which greatly limits its practicability especially in embedded systems. By leveraging the flexibility and high degree parallelism offered by reconfigurable...
Modern top of the line FPGAs can already host hundreds of simple soft-core processors. Because soft-cores often support floating point units through external interfaces this opens the door to explore the convenience for sharing the floating point units among a number of processors in many-soft-cores. We build two variants of a many-soft-core with 16 NIOSII cores to test if sharing the FPU gives an...
Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don't care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don't care set...
Partial reconfiguration (PR) enhances traditional FPGA-based systems-on-a-chip (SoCs) by providing benefits such as reduced area requirements and increased system flexibility. In multi-application PR SoCs, a dynamic resource manager (DRM) must efficiently orchestrate PR hardware resource management (access to and sharing of PR resources) in order to minimize the percentage of wasted/unused PR resources...
Over the past decades, we noticed huge advances in FPGA technologies. The topic of floating-point accelerator on FPGA has gained renewed interests due to the increased device size and the emergence of fast hardware floating-point library. The popularity of FFT makes it easier to justify spending lots of effort doing detailed optimization. However, the ever increasing data size in some compelling application...
In this paper, we propose a novel mapping method for FPGA with dual-output LUT based logic elements (LEs), aiming for power reduction. Recently, a new kind of LE-Adaptive Logic Module (ALM), which contains a dual-output fracturable LUT instead of traditional single-output K-LUT, is used in Altera's high-end FPGA products to obtain a good trade-off between area and delay. To map a design to ALMs, we...
Many studies have been directed to probe ring oscillator PUF's feasibility in the security field, but most of them suffer from the lack of global approach as they analyze the system isolated, giving an uncompleted theory about their behavior. This paper presents how adjacent hardware elements may affect PUF response, modifying their statistical characteristics and even masking the randomness of manufacturing...
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