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The recent emergence of 3D partially reconfigurable FPGAs implies that we need efficient online hardware task scheduling and placement algorithms for such architectures. However, the algorithms available in the literature for 3D FPGAs create a “blocking-effect”. That is, these algorithms tend to make a wrong decision in finding a location of each arriving hardware task during runtime scheduling and...
Due to the runtime flexibility of modern dynamically reconfigurable SRAM-based FPGAs, FPGA devices have become an attractive platform for developing system-on-chips (SoCs) for space applications (space SoCs). However, since the FPGA's SRAM is highly susceptible to space radiation, system reliability is a primary concern for space SoCs. To maintain system reliability and mitigate space radiation effects,...
Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. These phenomena can shift the threshold voltage of transistor over time, increase their delays and cause timing failure and ultimately reduction of lifetime of VLSI chips. As much as FPGAs benefit from the most scaled...
In this paper, we propose a reconfigurable macro-pipelined systolic architecture (MAPS), which aims to accelerate multiply-accumulate based algorithms by exploiting the temporal parallelism. To illustrate the performance, we implement a 32-PE accelerator on the Xilinx ML605 experiment board for the matrix multiplication and get a peak performance of 51.2 GFLOPS (about 8.0 GFLOPS per PE per GHz). To...
Exploiting the benefits afforded by runtime partial reconfiguration (PR) on modern field-programmable gate arrays (FPGAs)requires PR-capable applications and associated PR-architectures, both of which are challenging tasks due to competing implementation metrics(e.g., area, power, operating frequency, etc.) and results in unmanageable design spaces. PR design space exploration (DSE) techniques and...
A power-consumption-centric assignment algorithm called partially fixed configuration mapping (PFCM) is proposed for multi-context dynamically reconfigurable processors. By assigning the same operations into the same PE (processing element) as many as possible, the amount of changing configuration data for dynamic reconfiguration can be reduced, resulting in the redundant power consumed for changing...
Trusted computing is gaining an increasing acceptance in the industry and finding its way to cloud computing. With this penetration, the question arises whether the concept of hard-wired security modules will cope with the increasing sophistication and security requirements of future IT systems and the ever expanding threats and violations. So far, embedding cryptographic hardware engines into the...
The goal of this work is to model and predict timing failure rates of digital blocks in FPGAs due to delay variation. The timing failures are modelled as transient faults depending on the input vectors to the block, as opposed to conventional critical path failures. Firstly, we present transition tables derived from the truth tables of the logic gates which are apt for our purpose. Next we present...
CMA (Cool Mega Array) is an ultra low-power reconfigurable accelerator with a large PE (Processing Element) array consisting of combinational circuits. Although the configuration is static during execution, various types of application can be implemented by using the versatile data manupilation instructions of the attached micro-controller. By using a real CMA-1 chip, we will demonstrate that CMA-1...
There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative...
In this paper, we present results of a comprehensive study devoted to the optimization of FPGA implementations of modern cryptographic hash functions using embedded FPGA resources, such as Digital Signal Processing (DSP) units and Block Memories. Fifteen hash functions, including the current American hash standard SHA-2 and 14 candidates for the new hash standard SHA-3, have been included in our investigation...
Adaptive systems have the ability to respond to environmental conditions, by modifying their processing at runtime. While this is easy to do software systems, modern algorithms can be computationally expensive, requiring powerful processors. At the same time hardware is not as flexible. Field programmable gate arrays (FPGAs) are recognised as being suitable for adaptive systems implementation, due...
Embedded multicore devices require high performance with minimal power consumption; many systems use dedicated hardware units to meet these constraints. However, embedded systems have also become increasingly multi-purpose and must be able to execute a wide range of applications — some of which might not yet be known at design time. It is therefore difficult to choose an appropriate mix of dedicated...
In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves...
Connect6 is a new generation k-in-a-row game, which has drawn great interest not only from game enthusiasts, but also from researchers, due to its characteristics such as fairness and high state-space complexity. In this paper we describe the design and implementation of an FPGA-based Connect6 player that can compete against other computer-based opponents, communicating through a serial interface...
Ultrasound Imaging is one of the most widely used medical imaging methods, and beamforming is the enabling technology of ultrasound imaging, which directly influences the image quality. The critical problem of modern ultrasound imaging system is generating high resolution images at high frame rate. To solve this problem, real-time high precision beamforming delay parameters must be generated. This...
Efficient velocity estimation plays an important role in the stability of haptic interfaces. In this work, a new digital circuit is realized to reduce the noise level in low velocity estimation. The proposed adaptive-method (A-method) is based on the concept of measuring the time-interval between two or more incoming quadrature pulses from the optical encoder to the order of picoseconds (ps). A time-to-digital...
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