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Modern commercial Field-Programmable Gate Array (FPGA) architectures contain look-up-tables (LUTs) that can be “fractured” into two smaller LUTs. The potential of packing two LUTs into a space that could accommodate only one in traditional architectures complicates technology mapping's LUT minimization objective. Previous works introduced edge-recovery techniques and the concept of LUT balancing,...
Cryptographic message authentication is a growing need for FPGA-based embedded systems. In this paper a customized FPGA implementation of a GHASH function that is used in AES-GCM, a widely-used message authentication protocol, is described. The implementation limits GHASH logic utilization by specializing the hardware implementation on a per-key basis. The implemented module can generate a 128bit...
Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. These phenomena can shift the threshold voltage of transistor over time, increase their delays and cause timing failure and ultimately reduction of lifetime of VLSI chips. As much as FPGAs benefit from the most scaled...
There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative...
A method for generating high speed FIR filters with low complexity for FPGAs is presented. The realization is split into two parts. First, an adder graph is obtained using an existing multiple constant multiplication (MCM) algorithm. This adder graph describes the required multiplier block of the FIR filter using only additions/subtractions and shifts. Secondly, a novel FPGA-specific combined schedule...
In this paper, we propose a novel mapping method for FPGA with dual-output LUT based logic elements (LEs), aiming for power reduction. Recently, a new kind of LE-Adaptive Logic Module (ALM), which contains a dual-output fracturable LUT instead of traditional single-output K-LUT, is used in Altera's high-end FPGA products to obtain a good trade-off between area and delay. To map a design to ALMs, we...
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