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Actual MOS transistors models only use empirical models for the variation of the drain current in saturation. This is due to the bidimensional character of the MOS transistor channel. Gradual approximation can no longer be used for the whole transistor analysis due to the channel length modulation. But the gradual approximation still stands for the effective channel length of the transistor. And this...
The destruction mechanism in large area IGCTs (Integrated Gate Commutated Thyristors) under inductive switching conditions is analyzed in detail. The three-dimensional nature of the turn-off process in a 91mm diameter wafer is simulated with a two-dimensional representation. Simulation results show that the final destruction is caused by the uneven dynamic avalanche current distribution across the...
This paper presents a fully protected high side switch design from the short circuit perspective. The high side switch is dual configurable: either 7 Ω or 2 Ω in terms of ON resistance, each with its short circuit current limitation level. The circuit was implemented in a BCD technology, where the key for area efficiency is making use as much as possible of the low voltage components. This is especially...
The gate and bulk resistances influence on the impedance matching in case of MOSFET common gate amplifiers is investigated. It is shown that using a supplementary resistance of maximum 100Ω, S11 becomes less than −15 dB over a wide frequency range, therefore making the circuit suitable for low power wideband RF applications and less sensitive to the loading capacitor value, at the price of a supplementary...
Avalanche multiplication has been one of the major destructive failure mechanisms in IGBTs; in order to avoid operating an IGBT under abnormal conditions, it is desirable to develop peripheral protecting circuits monolithically integrated without compromising the operation and performance of the IGBT. In this paper, a monolithically integrated avalanche diode (Dav) for 600V Trench IGBT over-voltage...
A brief presentation of the NOI — Nothing On Insulator — nanotransistor, followed by two theoretical points of view concerning the NOI-FET non-linearity are presented in this paper. The main target is to prove the NOI nanotransistor affiliation to the FETs family, monitoring the gate-control on the drain current. The drain current is activated by the VDS voltage under tunneling conditions. The gate...
Single-Event-Burnout (SEB) is a catastrophic failure mode in power semiconductor devices triggered by cosmic ray heavy ions. Thus, it is essential to improve the robustness of these devices under this environment. In this paper a new design of planar insulated gate bipolar transistor (IGBT) aimed at improving the immunity to SEB is proposed and validated by employing 3D Sentaurus — simulation. We...
This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the reproducibility of the process, devices having the slit width ranging from 16 nm to 400 nm were fabricated, with slit conductance in the range 0...
In this paper we present a unity-gain follower amplifier based on a gated diode operated in breakdown regime in common cathode configuration. The amplifier has only one stage and it provides power amplification, high input impedance and a low output one. The maximum frequency that can be applied on the entrance of the amplifier so that the output remains undistorted is dependent on the bias current...
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