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Driver circuit of the small Liquid Crystal Display (LCD) is formed on the same glass substrate as LCD by means of the so-called SoG (System on Glass) technology. The timing pulse generator of LCD driver, which is to generate trigger signals for driving each pixel, is usually laid out restrictedly in an area remaining after the layout of other subcircuits in LCD driver. Thus, if the design automation...
During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable...
Nanoscale CMOS technologies, which were sensitive to electrostatic discharge (ESD), have been widely used to implement radio-frequency (RF) integrated circuits. Against ESD damages, ESD protection design must be included in RF circuits. A novel modified LC-tank ESD protection design was presented in this work. Such ESD protection circuit had been designed for 60-GHz RF applications and verified in...
With the thermal effect, improper analog placements may degrade circuit performance because the thermal gradient can affect electrical characteristics of the thermally-sensitive devices. To mitigate the thermal effect in analog layout design, it is required to reduce thermally-induced mismatches among matched devices in addition to eliminating thermal hot spots. This paper presents major challenges...
WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and...
Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine...
The design of integrated circuits involves the consideration of a large number of constraints of various types. In addition to the definition of these constraints in a constraint-driven design flow, the declaration of new, yet unknown constraint types might be necessary.
Pareto-optimal performance fronts have gained popularity as a representation of performance trade-offs of electronic circuits. They are also essential to support efficient bottom-up hierarchical design methodologies. Being such a key element in these methodologies, there have been many reported efforts to enhance the fronts with valuable information that goes beyond the nominal circuit behavior, such...
In this paper, a new method for developing smart parameterized generators for analogue devices is presented. A device is an atomic analogue cell that performs an elementary and standard function such as the differential pair and the current mirror. A device is smart since it can be electrically and physically adapted. In the proposed method, the device sizes and biases are first computed using dedicated...
In this paper a simple declarative language to define layout templates of analog circuits, named Layout Description Script (LDS), is introduced. In contrast to sequential description languages, coding constraints of a template is very easy with LDS. A methodology based on linear programming (LP) is presented to instantiate a layout from a set of LDS statements. Due to the LP formulation, area and...
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