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Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine...
Pareto-optimal performance fronts have gained popularity as a representation of performance trade-offs of electronic circuits. They are also essential to support efficient bottom-up hierarchical design methodologies. Being such a key element in these methodologies, there have been many reported efforts to enhance the fronts with valuable information that goes beyond the nominal circuit behavior, such...
In this paper a simple declarative language to define layout templates of analog circuits, named Layout Description Script (LDS), is introduced. In contrast to sequential description languages, coding constraints of a template is very easy with LDS. A methodology based on linear programming (LP) is presented to instantiate a layout from a set of LDS statements. Due to the LP formulation, area and...
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