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A two-transistor active pixel image sensor (2T-APS) architecture is proposed. Instead of a reset transistor, a diode within the pinned photodiode sensor is used to reset the charge-sensing node in each pixel without any extra area. The new architecture can be used to increase the fill factor and/or reduce the pixel pitch. A test structure of the 2T-APS has been demonstrated using 0.35 μm CMOS technology...
A new MIS Schottky-diode hydrogen sensor with La2O3 as gate insulator was fabricated. Its hydrogen-sensing properties were studied from room temperature (RT) to 300°C. Results showed that the device had excellent hydrogen-sensing performance below about 250°C.
This paper describes the development of a new class of solid state memory known as Storage Class Memory (SCM). We will examine various memory technologies that promise to become the emerging SCM standard currently under development in research laboratories and memory manufacturing facilities around the world. We will focus our attention mostly in the enterprise space and extrapolate the future of...
For the integration of high-density ferroelectric random access memories, each memory cell can be formed at the cross point of a plate line and a common node electrode, where the ferroelectric film is continuous between them. However, the peripheral region beyond the cross point of each cell without electrode coverage could also switch under the writing/reading pulse. To avoid this crosstalk problem...
The reverse generation current under high gate voltage stress condition in LDD MOSFET has been studied. It is found that the generation current peak decreases as the stress time increases. It ascribes to the dominating oxide trapped electrons in n-MOSFET and trapped holes in p-MOSFET which reduce the effective drain bias so that lowering the maximal generation rate. The density of the effective trapped...
A fully differential common-source cascode low noise amplifier(LNA) is presented for wireless receivers. The capacitive cross-coupling technique combined with cascode transistor is introduced to enhance LNA gain and reduce noise figure as well as the nonlinearity influence of cascaded transistors. A 2.6 mm long on-chip folded dipole antenna is integrated with this LNA and co-design is performed for...
A switchable dual-band low power low noise amplifier operated at 900MHz/1.95GHz has been designed for GSM/TD-SCDMA applications using 0.13 μm CMOS process. To achieve noise matching and input matching at both bands, a tunable capacitance bank and a switchable inductor for L-match are utilized. Four gain modes are accommodated with current splitting technique at the second stage. The post-layout simulated...
In this paper, an ultra-wideband low-noise-amplifier (LNA) is designed for low-voltage and multi-standard applications in 0.13 μm CMOS technology. Based on conversional resistive-negative-feedback structure, a novel feedback inductor technology is proposed. The presented LNA achieves a voltage gain of 14.7 dB, 2.95-4.1 dB noise figure from 0.5-10.6 GHz including test buffer. And the IIP3 is -7.2dBm...
Due to extreme miniaturization of device dimensions the well established TCAD tools are pushed to the limits of their applicability. Since conventional MOSFETs are already operating in the sub-100 nm range, new physical effects and principles begin to determine the transport characteristics and the validity of conventional current transport models is in question. The classical drift-diffusion model...
Space applications using advanced foundry processes require accurate assessment of the dependence of total-ionizing dose (TID) response on process variability and layout. A new test chip is described to enable large sample of device measurements under irradiation. The variability of TID-induced leakage current and transistor mismatch both increase after irradiation.
The method of using small-signal model to analyze jitter of the clock driver caused by thermal noise is presented. Multi-stage quasi-infinite load differential amplifier structure to effectively achieve low clock jitter is proposed. With transient noise simulation, jitter in the clock driver can be calculated. Through testing the SNR of ADC, The jitter of the designed clock driver in this paper is...
This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32÷32, one 32÷16, two 16÷16, four 8÷8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8÷8 Booth unit as the basic element, and longer bit modes...
In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages. A double poly triple metal 0.35 μm BiCMOS...
In this paper, we propose an efficient self-diagnosis approach to multi-channel systems with a single-wired connection technique to connect all speakers serially via sub controllers. The digital interface between the sub controllers and the main controller enables more robust control of sound quality and good channel expansion capability. The key technique of the proposed system is efficient bidirectional...
The charging characteristics of Sb nanocrystals embedded in organic semiconductor copper phthalocyanine (CuPc) have been studied for the first time. The images from atomic force microscopy show that Sb NCs grown on the surface of CuPc film exhibit a vertical height of 10-15 nm and uniform distribution, which are interspersed with a few bigger ones (~30 nm). Two kinds of capacitance-voltage measurements,...
We compare the switching behavior of two classes of resistive RAMs (RRAMs), namely Cu-SiO2 based conductive-bridging-RAMS (CBRAMs) and HfO2 based Oxide-RRAMs (OxRRAMs). In both devices the ON/OFF ratios are high, the set voltage is reproducible from cycle to cycle, and the reset voltage displays large dispersion. No forming stage is required in the investigated OxRRAMs. CBRAMs offer much lower programming...
A closed-loop controlled interface IC on the principle of force-balance for differential-capacitive sensor system is presented in this work. Signal buffer immune for the parasitic capacitors is introduced to reduce the signal attenuation. A novel PID compensation block is designed to enhance the stability of the system with extremely high gain for accuracy, which is realized with active feedback Op...
As the MOSFET's channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to doping fluctuation in the channel region. In this paper, a novel highly stable 10T SRAM cell is proposed which eliminates read SNM during read and write operation...
A smart temperature sensor based on 0.35um ASMC CMOS process with an inaccuracy of ±1°C from -55°C to 125°C is presented. The sensor uses substrate vertical bipolar transistor to measure the temperature and errors resulting from nonidealities in the readout circuit are reduced to 0.1°C level by applying dynamic element matching (DEM) and chopping offset cancellation techniques. By using pseudo-random...
In this paper, a preparation process of PCRAM access-diode-array with proprietary intellectual property rights (PIPR) is shown simply. Then, Relationship between device parameters and diode performance, including drive-current, breakdown, especially disturb-current, which influences the data-veracity and reliability of PCRAM, is analyzed from the views of carriers distribution and parasitic PNP-BJT...
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