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This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multiple security processors for cryptography are integrated in the SoC. Moreover, the performance can be greatly enhanced by the well-designed DTU (Data Transfer Unit), memory architecture...
A wide tuning range LC VCO with auto amplitude control is designed in 0.13-μm CMOS. Phase noise optimized design for the wide tuning range VCO is discussed and a PVT insensitive digitally reconfigurable auto amplitude calibration (AAC) circuit is used to stabilize the phase noise in the whole wide band. The proposed AAC circuit with a code estimated FSM provides faster operation to get the optimum...
A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1MHz signal and 100MHz sampling frequency...
A low-power single-channel sub-sampling 3-bit 4GS/s flash ADC in 0.13-μm CMOS is presented. Resistive averaging network and multi-stage interpolation technique are introduced for offset cancellation and power reduction, respectively. The comparator uses CML (current mode logic) blocks and pipelined structure to further enhance the speed of ADC. The simulation results reveal that the ENOB is 2.9 bit...
A low-power high-linearity PGA (Programmable Gain Amplifier) is proposed in this paper. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. This PGA is fabricated in TSMC 0.13um CMOS technology. The measurements show that the PGA provides 64dB (3dB~66dB) gain range with a step of 1dB, the...
A 6-GHz low-phase-noise voltage-controlled oscillator (VCO) is proposed. A varactor based coarse tuning method which differs from the traditional switch-capacitor based architecture is adopted. The source feedback resistors and a modified filtering technique are used to suppress low and high frequency noises of current source, respectively. To verify the concept, a prototype VCO is fabricated in 0...
A 0.13μm CMOS Direct-Conversion WiMAX/LTE transmitter with novel binary modulation gain control scheme and wide frequency band coverage is presented. In this work, binary modulation gain control realizes 36dB gain control at baseband frequency instead of by RF VGA at RF frequency. Output power is +0.5dBm and calculated EVM is 1.8%. A 4th order Butterworth low pass filter supports 2MHz~12MHz, 7-step...
This paper reports a Digitally Controlled Oscillator (DCO) with 20kHz frequency resolution. This is the first DCO implementing capacitor delta tuning and Dynamic Element Matching (DEM) to suppress process variations and mismatches between small capacitor deltas. The DCO is fabricated in 0.13μm CMOS IBM technology. The proposed DEM technique reduced the process variations and mismatches from 95% to...
A switchable dual-band low power low noise amplifier operated at 900MHz/1.95GHz has been designed for GSM/TD-SCDMA applications using 0.13 μm CMOS process. To achieve noise matching and input matching at both bands, a tunable capacitance bank and a switchable inductor for L-match are utilized. Four gain modes are accommodated with current splitting technique at the second stage. The post-layout simulated...
In this paper, an ultra-wideband low-noise-amplifier (LNA) is designed for low-voltage and multi-standard applications in 0.13 μm CMOS technology. Based on conversional resistive-negative-feedback structure, a novel feedback inductor technology is proposed. The presented LNA achieves a voltage gain of 14.7 dB, 2.95-4.1 dB noise figure from 0.5-10.6 GHz including test buffer. And the IIP3 is -7.2dBm...
This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32÷32, one 32÷16, two 16÷16, four 8÷8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8÷8 Booth unit as the basic element, and longer bit modes...
This paper presents a 6th-order Active-RC filter for multi-mode applications. The filter exploits Butterworth structure with digitally-controlled resistor and capacitor arrays, which is flexible for bandwidth tuning. The chip is fabricated in SMIC 0.13μm CMOS process, occupies an area of 0.83mm2. The measurement results indicate the filter provides a wide tuning range from 400kHz to 20MHz and achieves...
In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After...
A 2.4GHz receiver front-end with on-chip balun implemented with 0.13um CMOS technology is presented in this paper. Based on direct-conversion architecture, the front-end comprises a two-stage LNA (low noise amplifier) with optimized on-chip transformer and quadrature passive mixer. The gm-boosting technique is employed in 1st stage of LNA to achieve low noise and low current simultaneously. In 2nd...
A systematic methodology for opamp synthesis is presented. Based on this methodology, an automatic computer-aided design (CAD) tool called OTACAD is developed. OTACAD directly uses HSPICE as the simulator and a lookup table to model MOSFET in saturation region without complex equations. So it can design opamps in deep-sub-micron technologies and is suitable for various CMOS processes. Then, A sample...
A 2.4G-Hz high linear power amplifier (PA) with a parallel class A&B structure is presented. The self-biased cascode transistors are used to improve the reliability. The PA was fabricated in a 0.13-μm CMOS process. Measurement results show the power gain is 9.6dB and the output power at the 1dB compression point is larger than 10.6dBm under a single supply voltage of +3.3V. The measured IMD3 is...
In this paper, we designed a 1.2-V low supply voltage transconductance-C (Gm-C) low pass filter (LPF) for transmitter analog baseband front-end of wireless local area network (WLAN) transceiver applications. The filter's cut-off frequency is 10MHz and PIIP3 is 8.4dBm. The LPF uses a 3rd-order Chebyshev prototype. The filter is fabricated in TSMC 0.13-μm CMOS technology and drains 3.8mA from a 1.2-V...
An integrated 6.2-9.5GHz CMOS UWB receiver for WiMedia MB-OFDM is proposed. The fully differential receiver consists of a wideband LNA and a down conversion mixer with high and low gain mode. A low-pass filter and a programmable gain amplifier are also included. The chip was fabricated in TSMC 0.13-μm RF CMOS process. Measurement results show that the receiver achieves voltage gain from 21dB to 63dB...
Conventional solutions for dual-direction ESD protection have drawbacks in layout area (stacked unidirectional ESD clamps) and in process technology scaling (SCR-based solutions). To provide scalable protection, a new device architecture, based on a novel merged-collector dual-direction BJT-based ESD clamp, is proposed and successfully implemented in a 0.13 μm BiCMOS process.
A data frame synchronization sequence processor in HiNoC receiver is implemented in this paper. It is the important module for channel estimation and channel correction. 63-point FFT, phase extracting method and so on are presented considering hardware resource. The design has been fabricated with SMIC 0.13um technology.
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