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In this work, we studied current transport in mono-, bi-and tri-layer graphene. We find that both the temperature and carrier density dependencies in monolayer and bi-/tri-layers are diametrically opposite. These difference can be understood by the different density-of-states and the additional screening of the electrical field of the substrate surface polar phonons in bi-layer/tri-layer graphenes...
In this study, the electrical characteristics of high-k Tb2O3 polyoxide capacitors combined with rapid thermal post annealing have been improved (i.e.lower leakage current, higher electrical breakdown filed and lower electron trapping rate). The post-RTA annealing treatment can passivate and reduce trap states to terminate dangling bonds and traps in the high-k Tb2O3 dielectric and the interface between...
The 5-nm-thick HfO2 film doped with 35 mol% Gd2O3 (GDH) as a high k dielectric has been epitaxially grown on Si (100) substrate by pulsed laser deposition (PLD). In situ reflection high-energy electron diffraction (RHEED) evolution of the (100)-oriented GDH during the deposition has been investigated and shows that a two-dimensional (2D) single crystalline GDH grows with a smooth surface. The in-plane...
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
Based on MOS capacitors, this work aims to study the thermal and electrical characteristics of HfLaON with different nitridation treatments by evaluating the device properties and monitoring the induced changes.
An analytical model for high voltage Thin-film Silicon-On-Insulator (TSOI) lateral devices is proposed in this paper. A new Reduced SURface Field (RESURF) criterion is obtained for TSOI lateral devices with a lateral linear doping in the drift region. The optimum drift doping profile for TSOI lateral devices can be obtained from the new RESURF criterion. The analytical results are in good agreement...
In this paper, we report our approaches in realizing EOT of 0.5nm and below with rare earth La2O3 high-k gate dielectric. An EOT of 0.43nm was obtained from a TiN/W/La2O3(3nm)/n-Si capacitor by optimizing the thickness W layer. Our results show that a proper gate electrode is one of the most important factors for realizing EOT below 0.5nm.
We have investigated the role of oxygen in Hf-based high-k gate stacks on Vfb shift. It is clearly shown that the Vfb of the HfSiOx-based high-k materials of the weak ionic oxide was almost constant irrespective of the oxidation annealing temperature. On the other hand, the HfO2-based high-k materials of the strong ionic oxide caused the positive Vfb shifts by introducing additional oxygen into high-k...
Negative bias temperature instability (NBTI) recovery for pure-SiO2 and plasma-nitrided oxide (PNO)-based PMOSFET has been investigated at room and below temperature. It is found that the generated hole traps in SiON dielectric under NBTI stress has a broadened energy distribution than that in SiO2 dielectric. This broadened maybe due to nitrogen related traps (K center) In SiON. The traps' location...
The impact of FIB parameters on TEM sample preparation for the low-k dielectric values 2.7 in sub-65nm IC technology nodes is investigated. It is found that the condition of the ion beam and electron imaging has a strong effect on the profile of the low-k dielectric. Porous profile that enhanced by FIB was observed by TEM imaging. This phenomenon becomes more serious in the samples preparation by...
High-quality germanium oxynitride (GeON) gate dielectrics for Ge-based metal-oxide-semiconductor (MOS) devices were fabricated by plasma nitridation of ultrathin thermal oxides on Ge(100) substrates. Although ultrathin oxides with abrupt GeO2/Ge interfaces can be formed by conventional dry oxidation, air exposure results in serious electrical degradation. It was found that plasma nitridation forms...
A high voltage LDMOS on partial silicon-on-insulator (PSOI) with a variable low-k (relative permittivity) dielectric buried layer (VLKD) and a buried p-layer (BP) is proposed (VLKD BPSOI). In the vertical direction, the low k value enhances the electric field strength in the buried dielectric (EI) and the Si window makes the substrate share the voltage drop, which leads to a high vertical breakdown...
Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a physics-based picture that predicts the scaling of...
Integration of lanthanum lutetium oxide (LaLuO3) with a κ value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ~72 mV/dec and Ion/Ioff ratios up...
The principal obstacle to III-V compound semiconductors rivaling or exceeding the properties of Si electronics has been the lack of high-quality, thermodynamically stable insulators on III-V materials. For more than four decades, the research community has searched for suitable III-V compound semiconductor gate dielectrics or passivation layers. The research on ALD approach is of particular interest,...
Under white-light irradiation, thin film transistors based on copper phthalocyanine (CuPc) exhibited obvious hysteresis effects when applying bi-directional sweeping gate voltage, the hysteresis window comes up to 32 V. This hysteresis effect is the result of those accumulated photogenerated carriers trapped in the interface, which proposed a feasible way to detect the state of the interface between...
The electrical characteristics of a-IGZO thin-film transistors (TFTs) with HfO2 and HfON/HfO2/HfON (NON) tri-stack gate dielectrics are comparative investigated. Experimental results indicate that NON gate dielectric can effectively improve interface properties and enhance device reliability compared to HfO2 gate insulator. Bottom gate a-IGZO TFTs with NON gate dielectrics exhibit improved performance...
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