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This paper provides a comprehensive guideline to design high efficient Si thin film solar cells via surface periodic Si nanopillars (SiNP) array texturing. A power conversion efficiency of ~18.1% is predicted to be achievable for the cell consisting of the SiNP array (array periodicity of 500 nm, SiNP diameter of 250 nm, and SiNP length of 1000 nm) on 800 nm thick underlying Si film based on the optical...
A non-trivial nature of the power management circuit design is emphasized based on three case studies. The events of transient latchup and device failure under Charged Device Model (CDM) pulse due to an unexpected current path in power analog circuits are analyzed demonstrating the value of mixed-mode simulation approach.
A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1MHz signal and 100MHz sampling frequency...
A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement...
A low-power single-channel sub-sampling 3-bit 4GS/s flash ADC in 0.13-μm CMOS is presented. Resistive averaging network and multi-stage interpolation technique are introduced for offset cancellation and power reduction, respectively. The comparator uses CML (current mode logic) blocks and pipelined structure to further enhance the speed of ADC. The simulation results reveal that the ENOB is 2.9 bit...
In this paper, we propose a methodology of the automated bitstream generation for conducting high-testability FPGA tests. In order to study the efficiency of our solution we will explore our methodology in the test of an SOI-based FPGA. We use a semi-automated approach of the bitstream generation for ease of test vector design with high functionality and fault coverage. The methodology from this research...
SCMOS is a low cost, high capacity, high speed, high yield, and power saving VLSI device platform technology for microelectronics chips and modules. Benefits include: (1) Uses the complementary Low threshold Schottky Barrier Diodes (LtSBD or simply SBD). (2) Integrated the SBD and CMOS transistor as basic circuit elements for Analog, Logic, and Memory (ALM) macros. (3) Single power supply chip. Circuits...
Well-aligned ZnO nanorods were grown on the p-GaN substrate by a hydrothermal method and n-ZnO nanorods/p-GaN heterojunction LED structures were formed. The electroluminescence (EL) properties of this structure were studied under both forward and reverse bias. The nanorod LED device only has light output under reverse bias. The I-V characteristic results show that the nanosized junction can increase...
Space applications using advanced foundry processes require accurate assessment of the dependence of total-ionizing dose (TID) response on process variability and layout. A new test chip is described to enable large sample of device measurements under irradiation. The variability of TID-induced leakage current and transistor mismatch both increase after irradiation.
This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32÷32, one 32÷16, two 16÷16, four 8÷8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8÷8 Booth unit as the basic element, and longer bit modes...
A specific and high-sensitive immunosensor for detecting pulmonary tuberculosis (TB) markers in human serum is presented by miniaturizing array of microelectrodes via micro electro-mechanical system (MEMS) for multi-channel electrochemical measurement. The immunosensor is consisted of six Au disk working electrodes, one Au counter electrode and one Ag/AgCl reference electrode. Semi-insulating poly(o-phenylenediamine)(PoPD)...
This paper presents a new method to implement the Motion Compensation (MC) of AVS decoding process. An embedded coarse-grained reconfigurable processor, called Reconfigurable Multimedia System (REMUS) is used to complete this job. REMUS has been proved to be candidates for multimedia processing. The prominent advantage of REMUS is its high performance on calculation-intensive tasks, of which MC is...
At the present IC technologies, the accurately extraction of the interconnects parasitic parameters become more important. But for the time consuming, that computing the parameters of interconnects with field solver directly is impracticable. The common way is that establishing the pattern library according some typical Structures at the early design stage, then calculating the actual parameters after...
This paper presents a 10-bit 200MS/s CMOS current-steering digital-to-analog converter (DAC) with on-chip testbench. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. The measurement results show that the converter achieves a spurious-free dynamic range (SFDR) up to 78.7dBc. The full-scale output current is 20mA with 3V power supply for analog...
A new methodology of layout design applying Euler path is proposed. By separating the pFET array and nFET array away, and then mapping them to be diffusion graphs, we can reduce the operational complexity when solving Euler path and generating the stacked layout. The means that making use of adjacency matrix of diffusion graph to identify Euler path and adding dummy edge in advance could make Atallah...
A successive approximation register analog-to-digital converter(SAR ADC) targeted for use in RSSI(received signal strength indicator) is presented. The measured signal-to-noise-and-distortion ratios(SNDR) of the ADC is 53.95 dB at 1MS/s sampling rate with power consumption of 147.6 μW from 1.2-V supply voltage, thus the resulting FOM is 0.437 pJ/conversion-step. The ADC is fabricated in a 0.13-μm...
High speed, low power and compatibility with standard technology Static random access memory (SRAM) is essential for system on chip (SoC) technology. In this paper, we first present a 6T-SRAM (1WR) and two types of 8T-SRAM cell(2WR 1W1R). After that how the (1W1R) cell work with external unit is explained, and we compare the SNM sensitivity and the write/read operations time of 1WR 1W1R cell.
This paper presents a theoretical study on the possible realization of high frequency ultrasonic phased array transducer (f > 100 MHz) using MEMS technologies. A silicon based lithium niobate (LiNbO3) single crystal linear array is considered. Finite element method is employed for the simulation optimization design of such device. Continuous wave beam steering, focusing under different array and...
The design flow of a lumped Elements varactor-loaded Transmission-Line phase shifter (VLTL) is illustrated and a 60 GHz phase shifter of this kind is implemented in IBM 90nm CMOS process in this paper. The proposed VLTL is area-saving, occupying only 937um × 110um as it uses inductors instead of long transmission lines. This phase shifter is digitally controlled and need no extra DACs to realize phase...
For the past thirty years, the downscaling has been the guiding principle in the field of High-density semiconductor memories. However, recently, the limit of planar bulk MOSFETs is becoming apparent. Therefore, in order to extend the scalability of memory technology to the nano-scale generation, a new device structure is necessary. From the viewpoint, I will discuss future High density Memory with...
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