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A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and predicts the device performance trend induced...
We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
In this paper, we present an improved charge pump circuit for the non-volatile memories in RFID tags. The circuit consists of a single pumping branch without auxiliary capacitors and operates with a simple two-phase clock. The internal high voltages are used to control the gate and bulk terminals of the charge transfer switch. As a result, the threshold voltage loss and the leakage currents are eliminated...
In this article, an optimized transient performance CCL-LDO is proposed, which adopts the controlling method of the charge pump phase-locked loop. With 1μF decoupling capacitor, the experimental results based on 0.13μm CMOS process show that the output voltage is 1.0V, and when the workload changes from 100μA to 100mA transiently, the stable dropout is 4.25mV, settling time is 8.2μs and undershoot...
The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
In this paper, two novel structures at 200mV 0.18um sub-threshold full adders are proposed for wireless sensor network nodes or medical electronics. They use three state gate to enhance the transition time and drivability of carry out signal. Simulation results show that the transition time of the proposed structure using three state gate is 60% of that of old structure using transmission gate. The...
SCMOS is a low cost, high capacity, high speed, high yield, and power saving VLSI device platform technology for microelectronics chips and modules. Benefits include: (1) Uses the complementary Low threshold Schottky Barrier Diodes (LtSBD or simply SBD). (2) Integrated the SBD and CMOS transistor as basic circuit elements for Analog, Logic, and Memory (ALM) macros. (3) Single power supply chip. Circuits...
In this paper we overview recent attempts at co-integrating silicon nano-electro-mechanical systems (NEMS) with nanoelectronic devices aiming to add more functionalities to conventional electronic devices in `More-than-Moore' domain and also explore novel operating principles in `Beyond CMOS' domain.
The vacuum spacer transistors are compared with the conventional oxide spacer transistors in both high performance device and low standby power device. In high performance device case, with 14nm vacuum spacers, the CMOS inverter delay, switching charge, and switching energy are reduced by 6.6%, 15.6%, and 19.1%, respectively, compared to oxide spacer. In low standby power device case, with 18nm vacuum...
The nc-Si nonvolatile memory devices with high performance have been fabricated by using general CMOS techniques. High resolution transmission electronic microscope (HRTEM) shows that the average size of nc-Si is 8 nm and its density is 3×1011/cm2. The performance of programming/ erasing and retention time is mainly depending on the quality and thickness of tunnel layer and control layer. The results...
In this work, the metal gate effective work function (EWF) modulation for the TiN/Ta/TiN/SiO2/p-Si(100) structure was investigated. Comparing with TiN/SiO2/p-Si(100) structure, after annealing the introduction of Ta can effectively reduce the flat band voltage. It is also revealed that although as the thermal budget increases the flat band voltage obviously shifts toward the negative bias direction,...
A 2.4G-Hz high linear power amplifier (PA) with a parallel class A&B structure is presented. The self-biased cascode transistors are used to improve the reliability. The PA was fabricated in a 0.13-μm CMOS process. Measurement results show the power gain is 9.6dB and the output power at the 1dB compression point is larger than 10.6dBm under a single supply voltage of +3.3V. The measured IMD3 is...
TaN was widely used as Cu diffusion barrier in CMOS Cu-BEOL technology, in which it was removed by CMP process. Some work was done on TaN etch by Br/Cl-based gas for metal gate application. But seldom work was done for TaN etch in CF-based gas. In this work TaN etching in CF4/CHF3 gas was investigated on CVD alpha-Si substrate for CMOS compatible MEMS/Sensor application. To avoid resist poisoning...
A 1.8 V-to-10 V high-voltage tolerant level shifter (HVT level shifter) is presented in this paper. This new topology of HVT level shifter makes all the transistors working in safe operating region, and consequently greatly enhances the circuit's reliability. It has been fabricated in 0.18 μm CMOS process, and successfully integrated in an embedded EEPROM memory with 10 V programming/erasing voltages...
Stack-transistor structure is often used in RF applications for higher power handling capability and/or isolation. LDMOSFET may provide similar advantages with smaller device area and lower series resistance. The purpose of this work is extracting the RF parameters of a LDMOSFET and design a RF switching circuit with these parameters. The design trade-off between LDMOS and CMOS technologies was discussed...
CMOS compatible power devices have been an intensely pursued area in the past few decades. Power integrated circuit technologies are now accessible by many designers via popular foundry services. This paper is a brief review on modern integrated power transistors including the recently introduced CMOS compatible Orthogonal Gate extended drain MOSFETs (OG-EDMOS) and the lateral superjunction power...
With the technology scaling down to the deep sub-micron domain, leakage power increases rapidly in VLSI, enhancing the area overhead of dynamic power management system. Reverse Body Bias(RBB) is a common method to reduce the leakage power at run-time. To overcome the larger area overhead of controller applied on RBB, this paper proposes a new way of connection, which can reduce area of controller...
In this paper, a novel non-classical CMOS inverter with simple process and high integration density is proposed, which is composed of a junctionless NMOSFET and a gated N--N-N+ transistor for driver and load, respectively. Also, the gated N--N-N+ transistor performance is also investigated. Based on the numerical simulations, we find out that the carrier mobility of the gated N--N-N+ transistor is...
So far the most aggressive manufacturing forecast for 22nm technology node is in late 2011, and there still remains many arguments for its next generation, 15nm manufacturing technologies. The major obstacles in front of the manufacturing are (1) high cost fine patterning technology, (2) tradeoff of SRAM cell size and performance, (3) increasing variability, (4) short channel effect control, etc....
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials on the Si platform can provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. In this presentation,...
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