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We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices. A novel capacitor-less DRAM cell based on floating junction gate (FJG) concept can be configured with TFET. In addition, several different memory...
By analyzing the switch-signal theory and the principle of adiabatic circuits, a design scheme of Quaternary Clocked Transmission Gate Adiabatic Logic (QCTGAL) circuit is proposed in this paper. First the scheme by using switch-signal theory and switch-control technology of multithreshold MOS derive the switch level structure of Quaternary Adiabatic Literal Operation (QALO) circuits and Quaternary...
An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier...
The transient effect of graded channel partially-depleted silicon-on-insulator nMOSFETs are analyzed by SILVACO ATLAS software. The switch on and switch off transient behaviors are studied for the device. While the device operates in the kink region, the transient effects of drain current were also investigated. It was found that the transient characteristic of the graded channel device was superior...
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
Ultrathin (11 nm) strained SiGe-on-insulator (SGOI) with a Ge fraction of 0.5 was fabricated by Ge condensation technique. The residual compressive strain as high as 1.72% was achieved in SGOI layer by reducing the initial thickness of as-grown Si0.93Ge0.07 layer. Strained-SGOI pMOSFET exhibits a hole mobility of 3 times higher than that of Si-on-insulator pMOSFET.
This paper designs a 10th order switched-capacitor (SC) band-pass filter and its 6th order active-RC low-pass smooth filter. The center frequency and -3dB pass bandwidth of the SC filter are respectively 50kHz and 10kHz. The filters are used in a low-frequency communication system. At low frequency, the MOSFETs have large flicker noise. This paper designs an optimized low noise full differential op...
The reverse generation current under high gate voltage stress condition in LDD MOSFET has been studied. It is found that the generation current peak decreases as the stress time increases. It ascribes to the dominating oxide trapped electrons in n-MOSFET and trapped holes in p-MOSFET which reduce the effective drain bias so that lowering the maximal generation rate. The density of the effective trapped...
In the last years the MOS transistor technology has reach very high cut-off frequencies (near to 500 GHz), thanks to the continuous reduction of the channel length, but the short-channel-effects (SCE) strongly affects the MOSFET behavior below 60 nm. For such technology nodes the Multiple-Gate transistor (MuGFET) appears as a promising alternative to continue with the International Technology Roadmap...
The paper describes the parasitic structures of MOS transistors in SOI CMOS ICs at first. Then the influences of the parasitic structures on single particles radiation effect of MOS transistors in SOI CMOS ICs are presented. Finally the hardness methods of single event effects resulted by the parasitic structures of MOS transistors are given and the estimate about their excellence is made out.
In this paper, we propose a junctionless vertical MOSFET (JLVMOS) based on bulk-Si wafer. According to the numerical simulations, the proposed JLVMOS can get a steep subthreshold swing (S. Swing), reduced DIBL, and higher ION/IOFF ratio, in comparison to a junctionless planar SOI MOSFET. This is because the vertical double-gate (DG) structure truly helps reduce the short-channel effects (SCEs). More...
The dual-material gate and asymmetrical halo structure is used in surrounding gate MOSFET to improve the performance. By treating the device as three surrounding-gate MOSFETs connecting in series and maintaining current continuity, a comprehensive drain current model is developed for it. It is concluded that the device also exhibits increased current drivability and improved hot carrier reliability...
Based on Brokaw bandgap cell, an improved implementation of BGR which consists of a temperature compensated circuit and a simple feedback loop circuit is presented. The circuit exploits a high-order compensation method to realize a low TC and uses an op-amp-avoided feedback loop circuit to save the power dissipation. Implemented in 0.5μm BCD process, the proposed circuit achieves a TC of 1.9 ppm/°C...
The metal-oxide-semiconductor field-effect transistor (MOSFET) with a surrounding-gate (SG) is investigated. Poisson's Equation (PE) is solved analytically. The analytic expressions for electrical potential and threshold voltage (Vth) are obtained. The results are verified with Sentaurus simulations, good agreement is observed. The Vth model can be used for the integrated circuit designers.
Ultra-high-vacuum (UHV) deposited Ga2O3(Gd2O3) [GGO] has been employed for passivating InGaAs and Ge, without using any interfacial paissivation layers (IPLs). The GGO/InGaAs and /Ge metal-oxide-semiconductor capacitors (MOSCAPs) have exhibited low capacitance-equivalent-thickness (CET) of less than 1nm in GGO, low interfacial densities of states (Dit's) ~ 1011eV-1cm-2, and thermal stability at high...
In this paper, a novel non-classical CMOS inverter with simple process and high integration density is proposed, which is composed of a junctionless NMOSFET and a gated N--N-N+ transistor for driver and load, respectively. Also, the gated N--N-N+ transistor performance is also investigated. Based on the numerical simulations, we find out that the carrier mobility of the gated N--N-N+ transistor is...
In UHF RFID tag IC, multiple charge-pump stages are needed to form a rectifier for achieving a sufficiently high output voltage to supply the other circuit blocks. To save chip area and achieve a high output voltage simultaneously, the number of charge-pump stages should be optimized in accordance with the amplitude of the RF input signal. In this paper, an analysis on the relation between the output...
1T1R-architecture devices were fabricated by integrating ZrO2 based crossbar structure ReRAM onto a foundry-built MOSFET platform. Multilevel operation was realized by using the current limit of a selected cell transistor in the set process. The current level was determined by the transistor's gate voltage, resulting in the control of electrical resistance of the filamentary conductive paths in the...
Defects in SiGe-On-Insulator (SGOI) fabricated using Ge condensation by dry oxidation method were characterized by optical and electrical methods. The locations of main defect levels were determined to be above mid-gap for SGOI with low Ge fraction (Ge%), which tend to valance band direction and unintentionally induce high hole concentration in SGOI with increasing Ge%. The suppression of defects...
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