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This paper presents a low-offset, low-power, high-speed comparator using bulk biasing calibration technique. The adjustment of bulk voltage is realized by analog integration in a feedback loop. The technique can calibrate the offset voltage to small value without reducing speed. The comparator is designed in a standard digital 65nm CMOS technology with 1V supply voltage. The comparator works at 1GHz...
A multiloop method is presented for highly nonlinear ring oscillators in this paper. This circuit permits lower tuning gain through the use of coarse/fine frequency control, which also translates into a lower sensitivity to the voltage at the control lines. A 8-GHz VCO in SMIC 0.18μm 1P6M CMOS technology is designed. The linear tuning range of VCO is from 7.95 to 8.45GHz with the tuning voltage vary...
This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and predicts the device performance trend induced...
We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
A single-loop second-order 3 bits ΔΣ modulator in 180 nm standard CMOS is presented. The design is intended to achieve high linearity in low-voltage low-power environment. The modulator achieves 89-dB SNDR and 98-dB SFDR in 20Hz~16kHz signal bandwidth, while the power consumption is 210 μW under 1-V supply voltage.
In this paper, we present an improved charge pump circuit for the non-volatile memories in RFID tags. The circuit consists of a single pumping branch without auxiliary capacitors and operates with a simple two-phase clock. The internal high voltages are used to control the gate and bulk terminals of the charge transfer switch. As a result, the threshold voltage loss and the leakage currents are eliminated...
In this article, an optimized transient performance CCL-LDO is proposed, which adopts the controlling method of the charge pump phase-locked loop. With 1μF decoupling capacitor, the experimental results based on 0.13μm CMOS process show that the output voltage is 1.0V, and when the workload changes from 100μA to 100mA transiently, the stable dropout is 4.25mV, settling time is 8.2μs and undershoot...
Nanotube electronics still faces significant challenges such as integration/assembly, co-existence of metallic and semiconducting nanotubes, and air-stable n-type nanotube transistor for complementary circuit operation. Here we report our solutions to these major obstacles, which may eventually lead to realistic and scalable nanotube integrated circuits. We report the wafer-scale synthesis, transfer...
A design of barometric pressure sensor is presented in this paper, which is compatible with the standard CMOS process, and can solve the problem of the electrode feed-through out of the sealed cavity at the same time. Both electrodes of the sensor are leaded from the top side of the chip. When the initial gap of both electrodes formed the capacitor is 0.5 μm, and the side length of the square membrane...
In early days, our project team has analyzed the electric field, threshold voltage, capacitance, cut-off frequency and other characteristics of the double doping polysilicon gate MOSFET (DDPG-MOS), see references. In this study, the process steps of DDPG-MOS are designed and simulated with software TSUPREM. Then the frequency and transient characteristic of the device are analyzed using software MEDICI...
A wide tuning range LC VCO with auto amplitude control is designed in 0.13-μm CMOS. Phase noise optimized design for the wide tuning range VCO is discussed and a PVT insensitive digitally reconfigurable auto amplitude calibration (AAC) circuit is used to stabilize the phase noise in the whole wide band. The proposed AAC circuit with a code estimated FSM provides faster operation to get the optimum...
For transistor research and development, one of the important figures of merit is the carrier mobility. The measurement of mobility is cumbersome in large devices, and nearly impossible in nano scale devices. Very often, effective mobility (μeff) is extracted from the I-V curve instead. There are many pitfalls in equating μeff to mobility (μ), including charge-trapping and series resistance effects...
The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1MHz signal and 100MHz sampling frequency...
A compact automatic gain control (AGC) loop for GNSS RF receiver is presented in this paper. The proposed AGC loop circuit achieves higher integration and lower power by eliminating the bulky off-chip capacitor and charge pump circuit, which are widely used in traditional AGC. The proposed AGC consists of a programmable gain amplifier (PGA), a 2-bit flash analog to digital converter (ADC), and a novel...
This paper described a digitally controlled Buck converter. In this converter, the compensator implements the classic linear PID control law by the fixed-point algorithm. A proposed verification method is performed in Simulink environment. The structure of low area and power cost Ring ADC and high resolution DPWM is also introduced, respectively. The consistent mathematic and Spice simulation result...
This paper presents a novel first-order temperature compensated current reference. The measured temperature coefficient of this current reference is less than 290 ppm/°C over the temperature range from -20°C to 110°C. What's more, it is compatible with standard CMOS technology, which makes its application more flexible.
Ultra-thin SOI wafer technologies designed for 22/20nm CMOS are presented. It is stressed that planar, non-doped, and fully-depleted (FD) SOI structures are realistic options that not only solve various scaling issues, but also provide simplicity and flexibility in the device process and the circuit design. To realize 22/20nm planar FD-SOI CMOS, 300mm SOI wafer process by Smart Cut™ [1] has been optimized,...
A highly integrated 0.13um CMOS direct conversion transmitter front-end for wide-band code division multiple access (WCDMA) is presented. The transmitter delivers +6.8dBm output power while consuming 39mA. The overall gain can be programmed in 6dB steps over a 66dB range with 0.1dB accuracy. The transmitter front-end achieves an OIP3 with +19.2dBm, an error vector magnitude of 3.7%, and an adjacent...
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