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In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Non-preemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is...
Network-on-Chip (NoC) has been proposed as a paradigm for the network, wireless and multimedia applications executing on embedded chips with massive data processing. It requires high speed data transferring and low power consumption, and then efficient and accurate performance estimation tools are needed for system level optimization and analysis in a flexible way. In this paper, a new NoC simulator...
In this paper, a high thermal stable TaOx-based RRAM device has been fabricated with TiN as the top electrode. The fabricated device shows good endurance behavior with little fluctuations in voltages and resistance state. Due to the stability of this device, potential for MLC application was also investigated. In addition, the mechanism of the high performance of the device is analyzed with Gibbs...
Typical bipolar resistive switching behavior are observed in the In/poly-Fe2O3/Nb-SrTiO3 (Nb-STO) devices. Rectifying I-V characteristics along with switching ratio significantly related to the polarity of read voltage have been found. A negative read voltage remarkable enhances the switching ratio to 107 comparing with 102 for the positive polarity, which demonstrates an efficient way to improve...
The nanoscale (EOT<;6 nm) flash and resistive switching memories using IrOx nanocrystals have been investigated. The IrOx nanocrystals embedded in high-κ Al2O3 film are observed by both high-resolution transmission electron microscopy and x-ray photoelectron spectroscopy. The average size and density of IrOx nanocrystals are found to be ~3 nm and ~7×1012/cm2, respectively. The flash memory devices...
The transient effect of graded channel partially-depleted silicon-on-insulator nMOSFETs are analyzed by SILVACO ATLAS software. The switch on and switch off transient behaviors are studied for the device. While the device operates in the kink region, the transient effects of drain current were also investigated. It was found that the transient characteristic of the graded channel device was superior...
This paper presents a cell balancing management for battery pack. It is used for each cell in battery pack to protect pack from damages such as overheating and overvoltage taken by the different performances between different cells, it manages individual cell with CC-CV charging strategy, shunts charge current smoothly to protect every cell preferably; in order to be suitable for different charge...
The paper describes the design and implementation of a speaker driver applied to Class G/Class I with single phase power supply. Gain expanding and compressing technology are employed in signal processing circuit to optimize power dissipation. Experimental results using 0.18μm N-well CMOS show that it can obtain less than 0.006% THD at low power range and less than 0.4% at medium power range with...
The design highlight of a power amplifier (PA) for 3G and beyond handset applications is to maximize its power-added efficiency (PAE) with specified linearity requirement at both peak and back-off power levels. In addition to PAE, its cost and size are of very important design considerations among others. The design principle of a linear PA with good PAE is summarized. An overview of different GaAs...
Based on the application of high-speed, high-resolution A/D converter, this paper describes the design and implementation of a novel high-speed comparator. The comparator uses the high-speed, transmission delay stability technology, the auto-zero technology, and the cascade technology in order for the comparator to have the high-speed, high-resolution, transmission delay stability features. Its performances...
This paper describes the development of a new class of solid state memory known as Storage Class Memory (SCM). We will examine various memory technologies that promise to become the emerging SCM standard currently under development in research laboratories and memory manufacturing facilities around the world. We will focus our attention mostly in the enterprise space and extrapolate the future of...
A switchable dual-band low power low noise amplifier operated at 900MHz/1.95GHz has been designed for GSM/TD-SCDMA applications using 0.13 μm CMOS process. To achieve noise matching and input matching at both bands, a tunable capacitance bank and a switchable inductor for L-match are utilized. Four gain modes are accommodated with current splitting technique at the second stage. The post-layout simulated...
In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages. A double poly triple metal 0.35 μm BiCMOS...
We compare the switching behavior of two classes of resistive RAMs (RRAMs), namely Cu-SiO2 based conductive-bridging-RAMS (CBRAMs) and HfO2 based Oxide-RRAMs (OxRRAMs). In both devices the ON/OFF ratios are high, the set voltage is reproducible from cycle to cycle, and the reset voltage displays large dispersion. No forming stage is required in the investigated OxRRAMs. CBRAMs offer much lower programming...
The resistance switching characteristics of Cu doped HfO2 film are investigated for nonvolatile memory. Two stable states can be achieved under both pulse and DC electrical stress. Good performances including large storage window, fast operation speed, good endurance, and long time retention are shown in this device. The metallic filament is confirmed as the physical origin for resistance switching...
ADC is one of the key components employed in the digital controlled DC-DC converters. In this paper, a low power and high resolution algorithmic ADC is designed, which is suitable to the integrated digital controllers for high-frequency and low-power switched DC-DC converter. The designed 8-bit algorithmic ADC has 2 bits per stage. Simulation results show that ENOB up to 7.6bit is obtained. As one...
In this paper, a short-channel subthreshold swing model for three-terminal (3T) double-gate (DG) MOSFETs with Gaussian doping profile in the vertical direction of the channel is presented. The effective conduction path effect concept of uniformly doped DG MOSFETs is utilized to incorporate the doping dependency in the present model. The effect of varying peak doping position of Gaussian profile on...
The high breakdown voltage AlGaN/GaN HEMTs with source-terminated field plate was firstly fabricated for high frequency and high power application, employing by CF4 plasma treatment for enhancement-mode (E-mode). The results showed that by adding the distance of gate to drain, LGD from 5 um to 15um, the breakdown voltage of the device was rapidly increased 350V, whose value is from 50V to 400V while...
A novel polymer (organic) resistive memory device with the structure of W/parylene+Au/Al is presented in this paper. The organic memory device exhibits not only high scalability but also good compatibility with CMOS back-end process, for parylene is immune to the lithographic solvents. Moreover, parylene film could be fabricated by chemical vapor deposition (CVD) instead of spin-coating, thus the...
In this work we report the main results of a research activity on a novel device concept which aims to achieve a steep switching behavior based on the filtering of high-energy electrons in the FET source region. The filtering function is entrusted to a superlattice in the source extension, which could possibly be fabricated by depositing a number of appropriate semiconductor layers within the manufacturing...
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