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This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
The memory effect in floating nanodot gate field effect transistor (FET) was investigated by fabricating biomineralized inorganic nanodot embedded metal-oxide-semiconductor (MOS) devices. Artificially biomineralized Co oxide cores accommodated in ferritins were utilized as a charge storage node of floating gate memory. Two dimensional array of Co oxide core accommodated ferritin were, after selective...
In this work, we studied current transport in mono-, bi-and tri-layer graphene. We find that both the temperature and carrier density dependencies in monolayer and bi-/tri-layers are diametrically opposite. These difference can be understood by the different density-of-states and the additional screening of the electrical field of the substrate surface polar phonons in bi-layer/tri-layer graphenes...
The first material of silicon dioxide (SiO2) had been proposed as a chemical transducer element of pH sensitive membrane around the early of 1970s. In 1981 Matsuo et al. proposed Ta2O5 as pH sensing membrane. Start from that moment, many materials have been wildly investigated, e.g. Al2O3, SnO2, WO3. The rare -earth oxide, Samarium oxide (Sm2O3), is an attractive material to substitute the previous...
Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while...
PIN tunneling field effect transistor (TFET) is one of the most promising devices due to its low sub-threshold swing. In this paper, using TCAD simulation, we investigate the doping and structure dependence of the electric field in PIN TFET. We show that an insertion of a thin N layer into PIN structure (i.e., PNIN TFET) not only enhances the drive current but also improves the reliability of the...
The electrical transport behavior of carbon nanotube field-effect transistors (CNT-FETs) decorated with gold nanoparticles (NPs) has been investigated. After decoration with Au NPs, the Ion/Ioff ratios of nanotube FETs decrease and some of the p-type devices even change into metallic ones. The Au NPs decrease the contact resistances between the CNTs and metal electrodes, and accordingly increase the...
In this work we report the main results of a research activity on a novel device concept which aims to achieve a steep switching behavior based on the filtering of high-energy electrons in the FET source region. The filtering function is entrusted to a superlattice in the source extension, which could possibly be fabricated by depositing a number of appropriate semiconductor layers within the manufacturing...
In this paper, the C-V and I-V characteristics of Si-nanowire FET are presented. From the C-V data, the effects of undoped floating channel on the Si-nanowire FET are analyzed. Also, the intrinsic channel capacitance and mobility therein are extracted accurately by eliminating the effect of parasitic capacitances. Moreover, the I-V data free from the effect of the series resistance are obtained and...
A new methodology of layout design applying Euler path is proposed. By separating the pFET array and nFET array away, and then mapping them to be diffusion graphs, we can reduce the operational complexity when solving Euler path and generating the stacked layout. The means that making use of adjacency matrix of diffusion graph to identify Euler path and adding dummy edge in advance could make Atallah...
A SPICE-compatible circuit model for multi-sensor CDPS SENSE-FET (Current Detection and Power Self-Supply Sense Field Effect Transistor) is proposed. Based on the discrepancy in the current flow-lines, the subcircuit model is developed by employing the piecewise model equivalence. A dual-gate controlling model has been included to precisely describe the controllable charging current. Simulations,...
Based on the exact solution of the Poisson's equation, a new two-dimensional (2-D) model for the silicon-on-insulator (SOI) fully-depleted four-gate transistor(G4-FET) is successfully developed. The model is verified by its good agreement with the numerical simulation of the device simulator. For the threshold voltage degradation, it is found that the lateral coupling effects between lateral gate...
This paper summarizes our recent investigations of nano-wire n type tunneling field effect transistor (n-TFET) reliability by experimental measurements and physical analysis [1-3]. Large PBTI and HC degradations which are very different from those in conventional n-MOSFETs were observed. The results are interpreted by different degradation mechanism in TFET.
22nm node Si SOI Coplanar “N Channel Vertical Dual Carrier Field Effect Transistors” (VDCFET) and its SOC with effective channel length less than 10nm for communication applications are presented.
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