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A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm2 and consumes 81...
This paper demonstrates for the first time quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within...
A novel circuit switched swizzle network called XRAM is presented. XRAM uses an SRAM-based approach producing a compact footprint that scales well with network dimensions while supporting all permutations and multicasts. Capable of storing multiple shuffle configurations and aided by a novel sense-amp for robust bit-line evaluation, a 128×128 XRAM fabricated in 65nm achieves a bandwidth exceeding...
Magnetic feedback from a differential pair to the core of a cross-coupled oscillator reduces the effect of device losses, raising the oscillation frequency. Three prototypes using one-turn nested inductors and including on-chip downconversion mixers operate at 205 GHz, 240 GHz, and 300 GHz while drawing a power of 3.5 mW.
A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL...
A new chip ID generation method is presented that leverages the random and permanent characteristics of oxide breakdown. A 128b ID array is implemented in 65nm CMOS and two algorithms for stressing the oxides are presented, showing a near-ideal Hamming distance of 63.92 in silicon measurements and consistent IDs across voltage and temperature.
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is proposed for the first time. The asymmetric VTH shift is doubled from the conventional scheme without process and area penalty. Measurement results show 24% increase in SNM without write degradation by the asymmetric PG transistor. 70% read margin enhancement is achieved by the proposed...
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