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A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14μm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<;-83dBc...
This paper describes the implementation of a flexible Turbo and LDPC outer modem engine which is capable of supporting the WiFi(802.11n), WiMax(802.16e) and 3GPPLTE standard on the same hardware resources. The chip is implemented in a 65 nm CMOS technology and occupies 10.37 mm2. The decoder flexibility is offered by means of an application-specific instruction-set processor (ASIP), with full datapath...
A 4×45W (EIAJ) monolithic car audio power amplifier is presented that achieves a power dissipation decrease of nearly 2x over standard class AB operation by sharing load currents between loudspeakers. Output signals are conditioned using a common-mode control loop to allow switch placement between loads with minimal THD increase. A prototype is realized in a SOI bipolar-CMOS-DMOS process with 0.5μm...
This paper describes an activity-dependent intracortical microstimulation system-on-chip (SoC) that can convert extracellular neural signals recorded from one brain region to electrical stimuli delivered to another brain region in real-time. The system integrates an analog recording front-end with input noise voltage of 2.6μVrms in 10.5kHz bandwidth, 5.5μW 10b SAR ADC, 750nW digital spike discrimination...
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is proposed for the first time. The asymmetric VTH shift is doubled from the conventional scheme without process and area penalty. Measurement results show 24% increase in SNM without write degradation by the asymmetric PG transistor. 70% read margin enhancement is achieved by the proposed...
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