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3D promises a new dimension in composing systems by aggregating chips. Literally. While the most common uses are still tightly connected with its early forms as a packaging technology, new application domains have been emerging. As the underlying technology continues to evolve, the unique leverages of 3D have become increasingly appealing to a larger range of applications: from embedded/mobile applications...
We have studied key factors of Ti-based self-formed barrier technique on interconnect reliability. A performance of time dependent dielectric breakdown shows superior endurance, using quite a thin Ti-based self-formed barrier. However, to achieve a superior electromigration performance using Ti-based self-formed barrier, much more amount of Ti is needed compared with that of TDDB performance. This...
Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without...
Capacitance coupling in copper low-k interconnects can be further reduced by implementing Air gaps in the intra-layer dielectric. This paper describes the evaluation of an integrated Air gap technology using 32 and 22 nm node technology vehicles. Electrical, reliability, and yield results are presented.
A highly robust gap-fill process technology of spin-on glass (SOG) was developed for the interlayer dielectric (ILD) in sub-30 nm devices. We revealed that the filling behavior of SOG within gaps during spin-coating is mainly dependent on the capillary effect. The highly wettable surface treatment prior to SOG coating was found to enhance the gap-fill performance remarkably. This technique plays a...
In this paper we show that by shrinking MEMS switches to sub-micron thickness and a few microns in lateral dimension, they can be encapsulated in the dielectric spacer between the metallization of a back end CMOS process. By making zero restoring force rocker switches in addition to more traditional cantilever based switches we demonstrate that by coupling several switches together logic functions...
A trade-off property of CuSiN between EM improvement and line resistance increase was resolved by a breakthrough that leaves oxygen at grain boundary of Cu line surface before CuSiN formation. Then, the combination of CuSiN and Ti-rich TiN (Ti(N)) barrier metal (-BM) was applied. Oxygen left by weakening process strength of CuOx reduction lowered line resistance, because Si diffusion causing line...
The results of lifetime testing of Cu/Sn-Cu eutectic bonded dice at 10μm pitch in large area arrays of 325,632 interconnects are shown. The interconnect bonding process (pressure and temperature) required for the formation of low resistance (~100 mΩ), high yielding (99.99% individual bond yield), and reliable interconnects is described. The effects of thermal cycling on electrical yield and resistance...
We report on recent experimental studies performed as part of a 3D integrated circuit (3DIC) production-worthy process module roadmap check for 300 mm wafer-to-wafer (WtW) copper-to-copper thermocompression bonding and face-to-face (F2F) aligning. Specifically, we demonstrate submicron alignment capabilities (3sigma alignment variability ~ 1 μm) post Cu bonding on topography M1V1-to-M2 Cu wafers with...
As the integrated circuit industry is moving towards many-core architectures to combat the power wall, it faces an important challenge of providing inter-core interconnects that are low power and low latency, and offer large aggregate bandwidths. This paper presents an optimal design of network-on-chip interconnects in many-core architectures. A comprehensive optimization methodology is proposed that...
We examine the complex relationship between experimentally-measured power penalty performance metrics of a silicon photonic modulator, and its broad impact on the throughput performance of a full-scale on-chip optical interconnection network. Using our physically-accurate network-level simulation environment, we further evaluate this impact from hypothetical device performance improvements. The results...
Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material and process optimizations. This paper presents a frequency dependent analytical model including MOS effect of high aspect ratio TSV achieved in a full CMOS...
Lead-free flip chip package production solution for 40 nm technology node with aggressive ELK interconnect scheme and tight bump pitch of 150 μm is demonstrated. The use of LF bump and ELK dielectric in a same electronic component poses severe technical challenges due to the pronounced chip-packaging interaction in the system. In this paper, we reviewed the fundamental treatments to enhance the LF...
The reliable fabrication of interconnects containing ultra low-k organosilicate dielectrics (ULK) has been a significant technological challenge. ULK's are inherently fragile with reduced elastic constants. In addition, their Si-O backbone makes organosilicate films prone to moisture-assisted cracking leading to serious reliability concerns. In this study, we investigated the mechanical properties...
We have improved ELK film so that it is suitable for the processes used in fabricating Cu interconnects without using a dielectric protection layer for CMP, the so called “direct CMP process”. The depth profile of the pore size in the film was successfully controlled to prevent water absorption during the CMP process with a limited k-value increase in the film. The line-to-line dielectric breakdown...
This paper presents the first accurate AC impedance extraction methodology for the evaluation of high-frequency behavior of graphene nanoribbon (GNR) structures targeted for interconnect and inductor applications. To overcome the simplifying assumptions of Ohm's law that is invalid for high-frequency analysis of GNRs and to take into account the electric field variation within a mean free path, the...
With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene...
We present a modified Berman model that relates breakdown voltage distributions, from dual voltage ramp dielectric breakdown (DVRDB) test, to the distribution of time-to-fail (TTF) during constant voltage stress (CVS) conditions, assuming that dielectric failure behavior under a constant voltage stress follows the square-root E-model. The methodology presented in this work demonstrates a fast and...
We present results of a refined model that allows prediction of the influence of LER on the TDDB performance when scaling towards 20nm ½ pitch. The model is validated on 35nm ½ pitch state-of-the-art Cu/low-k interconnects, defined in a double patterning integration scheme, using wafer-level TDDB measurements and in-line post-CMP evaluation of both low-k space and parameters describing LER. The results...
High performance 32 nm-node interconnect with ELK (Extremely Low-k, k=3D2.4) has been demonstrated. To suppress process damage and enlarge the via-line space with a wide lithography process margin, robust ELK film with a metal hard mask (MHM) self-aligned via process has been developed. It has accomplished both ultimate low capacitance wirings and high TDDB reliability between Cu lines with vias....
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