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This paper describes a CMOS technology designed for static RAMs and microprocessors operating at 3.3 V. The technology features dual-work-function NFETs and PFETs that achieve 0.22 and 0.18 ??m minimum channel lengths, respectively. It also includes shallow-trench isolation, nitrided oxide for reliability, self-aligned titanium silicide diffusions and polysilicon, a damascene tungsten local interconnect,...
In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materials regarding to delay, environment and substrate sensitivity. Process optimization with selected materials...
The evolution of the active area/isolation transition has resulted in a modification of the isolation induced parasitic effects on the device. Using experimental results and simulations, we have analysed the corner parasitic transistor behaviour induced by an abrupt transition. We show that some technological parameters linked to the isolation process must be perfectly controlled for a good integration...
The presented smart sensor dimensioned for measuring pressures between 0 and 1000 mbar has been monolithically integrated on a single silicon chip. An efficient development of such sensor-systems can be done using two well-known techniques: ASIC design methodology and standard CMOS processing. Based on the cell library of a commercial semiconductor manufacturer, sensor-specific CMOS cells have been...
This paper describes a smart power bipolar-CMOS-DMOS (BCD) technology called BCD III designed at 1.2?? for single chip system integration. This technology, besides providing bipolar, CMOS and DMOS functions, offers the possibility to implement on the same chip EPROM and EEPROM non-volatile memories. A practical example of a complete system realized in a single chip solution using BCD III is also reported.
A newly developed BPSG filled deep trench isolation technology featuring trench formation at the end of the front end process is presented. A thick BPSG film is used as a trench filling material and interlayer dielectrics under-first level metal simultaneously. The process step counts in deep trench isolation process module is 70% smaller than that of a conventional process. The thick BPSG planarized...
This paper details the process features, device design and electrical characteristics for the lateral DMOS(LDMOS) and Bi-nMOS power devices that were implemented by the conventional 1.2??m, double metal CMOS process technology. The power devices, which were fabricated by the non-epi, self-isolation structure, allow the full compatibility with low-voltage analog/digital CMOS circuits on the same chip...
In this article we propose to use a combination of two optimization strategies, the Response Surface Model (RSM) method and the Levenberg-Marquardt (LM) method, for various optimization purposes in IC-technology. It is argued that both optimization techniques can be used complementary, combining the strenghts of both techniques while avoiding their weaknesses. As an illustration we apply this strategy...
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