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In this paper we report a physically based thin gate oxide MOSEET model for ULSI circuit simulations. It is shown that to accurately model current and capacitances in these devices down to 0.1??m channel length, one must use effective gate oxide thickness that is larger than the physical thickness in the classical MOSFET circuit models. The increase in the effective Tox from its physical value depends...
A generalized version of the small-signal drift-diffusion model accounting for trapped charge dynamics is presented; the explicit introduction of two new continuity equations for the trapped electrons and holes is avoided by incorporating them in the original three equations, thus allowing for easier implementation while mantaining the same degree of accuracy of the full system. Simulations carried...
Based on on-chip capacitance measurements, we have modelled MOS transistor gate capacitances consistently with Spice Meyer models. A summary of the On-Chip measurement principle is given together with experimental setup and test chip description. Experimental results obtained with a 1 ??m channel length MOS transistor demonstrate the limitation of electrical models for short channel devices even with...
The dependence of the gate capacitance Cgds on biasing voltages in currentless regime is discussed for nMOS and pMOS devices. The components of the overlap capacitance are extracted as well as the effective poly and channel length. The influence of processing conditions on the overlap capacitance is shown.
A flexible capacitive normal / shear force sensor design is presented. Fabrication on a flexible polyimide substrate allows the sensor to be molded to non-planar gripper surfaces. The ability to measure normal and shear forces will greatly advance the tactile sensing capabilities of articulated grippers. The structure of the sensor also provides the ability to integrate additional sensors into a tactile...
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