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Anomalous increase in Vts (NMOS Vt roll-up effect) with the decreasing gate length in sub-micron technologies is usually attributed to the lateral redistribution of doping near source and drain junctions, or to silicon interstitial capture in gate oxide. Our results demonstrate that the poly-Si gate doping level dominates the observed Vt rollup effect and suggest a simple method for its suppression.
This paper will describe the characterization and electrical optimization of a high performance Atomic Layer Engineered Sealed Interface Local Oxidation (ALESILO) field isolation process steps. This process uses a vacuum load-lock equipped cluster vertical furnace (fig. 1). That allows perfectly controlled nitride/silicon interface sealing avoiding any extra RTN step[1] to achieve 100 nm range bird's...
A novel process technology has been developed for "smart" analog and mixed-signal products requiring embedded EEPROM. The technology is a modular addition to a 0.8 μm, single polysilicon, double metal baseline CMOS process. The EEPROM process architecture is defined with the primary goal of minimizing the number of additional process steps driven by wafer cost considerations. A double polysilicon...
A high performance 0.35 μm CMOS technology is presented for low operating voltages. The increased reliability margin at low supply voltages was used to scale the gate oxide thickness and optimize the channel and source/drain junctions profiles. The resulting well controlled short-channel behaviour of the devices was used to obtain low leakage current at low threshold voltages. Good circuit performance...
CMOS SOI devices, realised on very thin silicon film on SIMOX material, are very attractive for ULSI application. There are many advantages over bulk that have been frequently emphasised in the literature [1]. For sub-quarter micron devices, there are several candidate architectures and device operations, depending on the gate material: - enhancement mode Partially or Fully Depleted devices, for a...
Fabrication of self-aligned silicide of CoSi2 on source/drain areas in a tungsten polycide (WSix/poly) process is demonstrated. CoSi2 is formed by RTA under conditions identical to the poly gate process, i.e. no extra capping layer is required on top of the WSix gate. The materials interactions of WSix with Co films during RTA and subsequent wet etching steps have been studied. Transistor results...
A characterization of the low frequency noise of Si MOS devices from a 0.35 μm CMOS technology after uniform gate stress and nitridation step is presented. It is found that stress alters noise spectra differently depending on the device area. The spectra can be increased uniformly or may be distorted after stress, indicating a net creation of interface traps. On the other side, nitridation is found...
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