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Anomalous increase in Vts (NMOS Vt roll-up effect) with the decreasing gate length in sub-micron technologies is usually attributed to the lateral redistribution of doping near source and drain junctions, or to silicon interstitial capture in gate oxide. Our results demonstrate that the poly-Si gate doping level dominates the observed Vt rollup effect and suggest a simple method for its suppression.
Fabrication of self-aligned silicide of CoSi2 on source/drain areas in a tungsten polycide (WSix/poly) process is demonstrated. CoSi2 is formed by RTA under conditions identical to the poly gate process, i.e. no extra capping layer is required on top of the WSix gate. The materials interactions of WSix with Co films during RTA and subsequent wet etching steps have been studied. Transistor results...
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